Lines Matching defs:bcs
43 jade_empty_fifo(struct BCState *bcs, int count)
46 struct IsdnCardState *cs = bcs->cs;
51 if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) {
54 WriteJADECMDR(cs, bcs->hw.hscx.hscx, jade_HDLC_RCMD, jadeRCMD_RMC);
55 bcs->hw.hscx.rcvidx = 0;
58 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
59 bcs->hw.hscx.rcvidx += count;
60 READJADEFIFO(cs, bcs->hw.hscx.hscx, ptr, count);
61 WriteJADECMDR(cs, bcs->hw.hscx.hscx, jade_HDLC_RCMD, jadeRCMD_RMC);
63 char *t = bcs->blog;
66 bcs->hw.hscx.hscx ? 'B' : 'A', count);
68 debugl1(cs, "%s", bcs->blog);
73 jade_fill_fifo(struct BCState *bcs)
75 struct IsdnCardState *cs = bcs->cs;
83 if (!bcs->tx_skb)
85 if (bcs->tx_skb->len <= 0)
88 more = (bcs->mode == L1_MODE_TRANS) ? 1 : 0;
89 if (bcs->tx_skb->len > fifo_size) {
93 count = bcs->tx_skb->len;
95 waitforXFW(cs, bcs->hw.hscx.hscx);
96 ptr = bcs->tx_skb->data;
97 skb_pull(bcs->tx_skb, count);
98 bcs->tx_cnt -= count;
99 bcs->hw.hscx.count += count;
100 WRITEJADEFIFO(cs, bcs->hw.hscx.hscx, ptr, count);
101 WriteJADECMDR(cs, bcs->hw.hscx.hscx, jade_HDLC_XCMD, more ? jadeXCMD_XF : (jadeXCMD_XF | jadeXCMD_XME));
103 char *t = bcs->blog;
106 bcs->hw.hscx.hscx ? 'B' : 'A', count);
108 debugl1(cs, "%s", bcs->blog);
117 struct BCState *bcs = cs->bcs + jade;
123 if (!test_bit(BC_FLG_INIT, &bcs->Flag))
132 if ((r & 0x40) && bcs->mode)
134 debugl1(cs, "JADE %c RDO mode=%d", 'A' + jade, bcs->mode);
143 jade_empty_fifo(bcs, count);
144 if ((count = bcs->hw.hscx.rcvidx - 1) > 0) {
150 memcpy(skb_put(skb, count), bcs->hw.hscx.rcvbuf, count);
151 skb_queue_tail(&bcs->rqueue, skb);
155 bcs->hw.hscx.rcvidx = 0;
156 schedule_event(bcs, B_RCVBUFREADY);
159 jade_empty_fifo(bcs, fifo_size);
160 if (bcs->mode == L1_MODE_TRANS) {
165 memcpy(skb_put(skb, fifo_size), bcs->hw.hscx.rcvbuf, fifo_size);
166 skb_queue_tail(&bcs->rqueue, skb);
168 bcs->hw.hscx.rcvidx = 0;
169 schedule_event(bcs, B_RCVBUFREADY);
173 if (bcs->tx_skb) {
174 if (bcs->tx_skb->len) {
175 jade_fill_fifo(bcs);
178 if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
179 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
181 spin_lock_irqsave(&bcs->aclock, flags);
182 bcs->ackcnt += bcs->hw.hscx.count;
183 spin_unlock_irqrestore(&bcs->aclock, flags);
184 schedule_event(bcs, B_ACKPENDING);
186 dev_kfree_skb_irq(bcs->tx_skb);
187 bcs->hw.hscx.count = 0;
188 bcs->tx_skb = NULL;
191 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
192 bcs->hw.hscx.count = 0;
193 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
194 jade_fill_fifo(bcs);
196 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
197 schedule_event(bcs, B_XMTBUFREADY);
205 struct BCState *bcs;
206 bcs = cs->bcs + jade;
215 if (bcs->mode == 1)
216 jade_fill_fifo(bcs);
221 if (bcs->tx_skb) {
222 skb_push(bcs->tx_skb, bcs->hw.hscx.count);
223 bcs->tx_cnt += bcs->hw.hscx.count;
224 bcs->hw.hscx.count = 0;
226 WriteJADECMDR(cs, bcs->hw.hscx.hscx, jade_HDLC_XCMD, jadeXCMD_XRES);