Lines Matching defs:state
187 static void setup_vbi(struct au8522_state *state, int aud_input)
192 au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_H_REG017H, 0x00);
193 au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_L_REG018H, 0x00);
194 au8522_writereg(state, AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H, 0x00);
195 au8522_writereg(state, AU8522_TVDEC_VBI_USER_TUNIT_H_REG01AH, 0x00);
196 au8522_writereg(state, AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH, 0x00);
197 au8522_writereg(state, AU8522_TVDEC_VBI_USER_THRESH1_REG01CH, 0x00);
198 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH, 0x00);
199 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH, 0x00);
200 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H, 0x00);
201 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H,
203 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H,
205 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H,
210 au8522_writereg(state, i, 0x40);
214 au8522_writereg(state, 0x44, 0x60);
218 au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_H_REG017H,
223 static void setup_decoder_defaults(struct au8522_state *state, bool is_svideo)
229 au8522_writereg(state, AU8522_TVDEC_SHARPNESSREG009H, 0x07);
230 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 0xed);
231 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 0x79);
232 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
233 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
234 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
235 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
238 au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
241 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x04);
243 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x00);
245 au8522_writereg(state, AU8522_TVDEC_PGA_REG012H,
247 au8522_writereg(state, AU8522_TVDEC_COMB_MODE_REG015H,
249 au8522_writereg(state, AU8522_TVDED_DBG_MODE_REG060H,
252 if (state->std == V4L2_STD_PAL_M) {
253 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
257 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
261 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
265 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
268 au8522_writereg(state, AU8522_TVDEC_VCR_DET_LLIM_REG063H,
270 au8522_writereg(state, AU8522_TVDEC_VCR_DET_HLIM_REG064H,
272 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR1_REG065H,
274 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR2_REG066H,
276 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR3_REG067H,
278 au8522_writereg(state, AU8522_TVDEC_COMB_NOTCH_THR_REG068H,
280 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR1_REG069H,
282 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR2_REG06AH,
284 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,
287 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
289 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
292 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
294 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
297 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,
299 au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,
301 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H,
303 au8522_writereg(state, AU8522_REG071H, AU8522_REG071H_CVBS);
304 au8522_writereg(state, AU8522_REG072H, AU8522_REG072H_CVBS);
305 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H,
307 au8522_writereg(state, AU8522_REG074H, AU8522_REG074H_CVBS);
308 au8522_writereg(state, AU8522_REG075H, AU8522_REG075H_CVBS);
309 au8522_writereg(state, AU8522_TVDEC_DCAGC_CTRL_REG077H,
311 au8522_writereg(state, AU8522_TVDEC_PIC_START_ADJ_REG078H,
313 au8522_writereg(state, AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H,
315 au8522_writereg(state, AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH,
317 au8522_writereg(state, AU8522_TVDEC_INTRP_CTRL_REG07BH,
319 au8522_writereg(state, AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H,
321 au8522_writereg(state, AU8522_TOREGAAGC_REG0E5H,
323 au8522_writereg(state, AU8522_REG016H, AU8522_REG016H_CVBS);
325 setup_vbi(state, 0);
338 au8522_writereg(state, filter_coef[i].reg_name,
344 au8522_writereg(state, AU8522_REG42EH, 0x87);
345 au8522_writereg(state, AU8522_REG42FH, 0xa2);
346 au8522_writereg(state, AU8522_REG430H, 0xbf);
347 au8522_writereg(state, AU8522_REG431H, 0xcb);
348 au8522_writereg(state, AU8522_REG432H, 0xa1);
349 au8522_writereg(state, AU8522_REG433H, 0x41);
350 au8522_writereg(state, AU8522_REG434H, 0x88);
351 au8522_writereg(state, AU8522_REG435H, 0xc2);
352 au8522_writereg(state, AU8522_REG436H, 0x3c);
355 static void au8522_setup_cvbs_mode(struct au8522_state *state, u8 input_mode)
358 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
362 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
365 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
367 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
369 setup_decoder_defaults(state, false);
371 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
375 static void au8522_setup_cvbs_tuner_mode(struct au8522_state *state,
379 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
384 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
387 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e);
390 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10);
393 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
395 setup_decoder_defaults(state, false);
397 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
401 static void au8522_setup_svideo_mode(struct au8522_state *state,
404 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
408 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
411 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
414 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
416 setup_decoder_defaults(state, true);
418 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
424 static void disable_audio_input(struct au8522_state *state)
426 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
427 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
428 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
430 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x04);
431 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0x02);
433 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
438 static void set_audio_input(struct au8522_state *state)
440 int aud_input = state->aud_input;
447 disable_audio_input(state);
460 au8522_writereg(state, lpfilter_coef[i].reg_name,
465 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
466 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
467 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
468 au8522_writereg(state, AU8522_I2C_CONTROL_REG1_REG091H, 0x80);
469 au8522_writereg(state, AU8522_I2C_CONTROL_REG0_REG090H, 0x84);
471 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x00);
473 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
476 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
477 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
478 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0xff);
480 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
481 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
482 au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO);
483 au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x82);
485 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x09);
486 au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03);
487 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0xc2);
494 struct au8522_state *state =
499 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH,
503 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH,
507 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
509 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
513 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
515 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
531 struct au8522_state *state = to_state(sd);
533 reg->val = au8522_readreg(state, reg->reg & 0xffff);
540 struct au8522_state *state = to_state(sd);
542 au8522_writereg(state, reg->reg, reg->val & 0xff);
547 static void au8522_video_set(struct au8522_state *state)
551 au8522_writereg(state, 0xa4, 1 << 5);
553 switch (state->vid_input) {
556 au8522_setup_cvbs_mode(state, input_mode);
560 au8522_setup_cvbs_mode(state, input_mode);
564 au8522_setup_cvbs_mode(state, input_mode);
568 au8522_setup_cvbs_mode(state, input_mode);
572 au8522_setup_svideo_mode(state, input_mode);
576 au8522_setup_svideo_mode(state, input_mode);
581 au8522_setup_cvbs_tuner_mode(state, input_mode);
588 struct au8522_state *state = to_state(sd);
592 * Clear out any state associated with the digital side of the
596 state->current_frequency = 0;
598 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
602 au8522_video_set(state);
603 set_audio_input(state);
605 state->operational_mode = AU8522_ANALOG_MODE;
609 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
611 state->operational_mode = AU8522_SUSPEND_MODE;
619 struct au8522_state *state = to_state(sd);
625 state->vid_input = input;
632 if (state->operational_mode == AU8522_ANALOG_MODE)
633 au8522_video_set(state);
640 struct au8522_state *state = to_state(sd);
645 state->std = std;
647 if (state->operational_mode == AU8522_ANALOG_MODE)
648 au8522_video_set(state);
656 struct au8522_state *state = to_state(sd);
658 state->aud_input = input;
660 if (state->operational_mode == AU8522_ANALOG_MODE)
661 set_audio_input(state);
669 struct au8522_state *state = to_state(sd);
673 lock_status = au8522_readreg(state, 0x00);
729 struct au8522_state *state;
741 /* allocate memory for the internal state */
742 instance = au8522_get_state(&state, client->adapter, client->addr);
760 kfree(state);
765 state->config = demod_config;
766 state->i2c = client->adapter;
768 sd = &state->sd;
771 hdl = &state->hdl;
788 kfree(state);
792 state->c = client;
793 state->std = V4L2_STD_NTSC_M;
794 state->vid_input = AU8522_COMPOSITE_CH1;
795 state->aud_input = AU8522_AUDIO_NONE;
796 state->id = 8522;
797 state->rev = 0;
800 au8522_writereg(state, 0x106, 1);