Lines Matching refs:status
333 int status = 0;
338 while (!status) {
351 status = WriteBlock(state, Address, Length * 2, pTable, 0);
354 return status;
373 int status;
377 status = WriteTable(state, state->m_InitCE);
378 if (status < 0)
386 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
387 if (status < 0)
390 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
391 if (status < 0)
394 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
395 if (status < 0)
398 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
399 if (status < 0)
404 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
405 if (status < 0)
408 return status;
413 int status = 0;
421 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
422 if (status < 0)
429 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
430 if (status < 0)
432 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
433 if (status < 0)
435 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
436 if (status < 0)
438 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
439 if (status < 0)
443 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
444 if (status < 0)
446 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
447 if (status < 0)
452 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
453 if (status < 0)
458 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
459 if (status < 0)
464 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
465 if (status < 0)
467 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
468 if (status < 0)
470 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
471 if (status < 0)
475 return status;
480 int status = 0;
484 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
485 if (status < 0)
489 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
490 if (status < 0)
492 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
493 if (status < 0)
497 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
498 if (status < 0)
502 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
503 if (status < 0)
506 return status;
541 int status;
545 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
546 if (status < 0) {
547 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
548 return status;
571 int status;
581 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
582 if (status < 0)
586 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
587 if (status < 0)
592 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
593 if (status < 0)
610 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
611 if (status < 0)
616 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
617 if (status < 0)
624 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
625 if (status < 0)
635 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
636 if (status < 0)
638 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
639 if (status < 0)
686 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
687 if (status < 0)
689 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
690 if (status < 0)
692 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
693 if (status < 0)
695 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
696 if (status < 0)
698 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
699 if (status < 0)
709 return status;
714 int status = 0;
727 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
728 if (status < 0)
737 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
738 if (status < 0)
741 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
742 if (status < 0)
748 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
749 if (status < 0)
755 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
756 if (status < 0)
762 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
763 if (status < 0)
779 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
780 if (status < 0)
783 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
784 if (status < 0)
790 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
791 if (status < 0)
796 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
797 if (status < 0)
807 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
808 if (status < 0)
814 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
815 if (status < 0)
830 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
831 if (status < 0)
834 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
835 if (status < 0)
841 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
842 if (status < 0)
848 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
849 if (status < 0)
855 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
856 if (status < 0)
861 return status;
866 int status = 0;
871 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
873 if (status >= 0) {
901 return status;
933 int i, status = 0;
964 status = WriteBlock(state, Address, BlockSize,
966 if (status < 0)
972 return status;
979 int status;
981 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
982 if (status < 0)
983 return status;
988 status = -1;
991 status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0);
994 if (status >= 0)
995 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
996 return status;
1001 int status = 0;
1014 status = Write16(state, HI_RA_RAM_SRV_CMD__A,
1017 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL);
1019 return status;
1032 int status;
1035 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
1037 if (status == 0)
1038 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL);
1041 return status;
1064 int status;
1076 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1077 if (status < 0)
1079 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1080 if (status < 0)
1082 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1083 if (status < 0)
1085 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1086 if (status < 0)
1088 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1089 if (status < 0)
1092 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1093 if (status < 0)
1098 if (status >= 0) {
1102 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1104 if (status < 0)
1111 return status;
1118 int status;
1122 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1126 return status;
1170 int status = 0;
1173 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1175 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1177 if (!(status < 0))
1178 status = WriteTable(state, state->m_ResetECRAM);
1179 if (!(status < 0))
1180 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1181 return status;
1188 int status;
1195 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1196 if (status < 0)
1200 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1201 if (status < 0)
1205 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1206 if (status < 0)
1210 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1211 if (status < 0)
1216 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
1217 if (status < 0)
1223 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1224 if (status < 0)
1228 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1229 if (status < 0)
1233 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1234 if (status < 0)
1238 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1239 if (status < 0)
1244 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
1245 if (status < 0)
1249 return status;
1254 int status;
1257 status = WriteTable(state, state->m_InitFE_1);
1258 if (status < 0)
1262 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1267 status = SetCfgPga(state, 0);
1269 status =
1275 if (status < 0)
1277 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
1278 if (status < 0)
1280 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
1281 if (status < 0)
1284 status = WriteTable(state, state->m_InitFE_2);
1285 if (status < 0)
1290 return status;
1308 int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0);
1309 if (status == 0 || curCmd == 0)
1310 return status;
1317 int status = 0;
1327 status = -1;
1330 return status;
1336 int status = 0;
1343 status = -1;
1354 return status;
1360 int status;
1364 status = SC_WaitForReady(state);
1365 if (status < 0)
1367 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1368 if (status < 0)
1370 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1371 if (status < 0)
1373 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1374 if (status < 0)
1377 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
1378 if (status < 0)
1382 return status;
1388 int status = 0;
1392 status = SC_WaitForReady(state);
1393 if (status < 0)
1395 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1396 if (status < 0)
1398 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1399 if (status < 0)
1403 return status;
1409 int status;
1481 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
1482 if (status < 0)
1484 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
1485 if (status < 0)
1487 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
1488 if (status < 0)
1490 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
1491 if (status < 0)
1494 return status;
1499 int status = 0;
1503 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1504 if (status < 0)
1507 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1508 if (status < 0)
1534 status = -1;
1540 if (status < 0)
1541 return status;
1586 return status;
1591 int status;
1605 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
1606 if (status < 0)
1608 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
1609 if (status < 0)
1666 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
1667 if (status < 0)
1671 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
1672 if (status < 0)
1678 return status;
1683 int status;
1691 status = DRX_GetLockStatus(state, &lock);
1692 if (status < 0)
1696 status = StopOC(state);
1697 if (status < 0)
1702 status = ConfigureMPEGOutput(state, 0);
1703 if (status < 0)
1708 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
1709 if (status < 0)
1712 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1713 if (status < 0)
1715 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1716 if (status < 0)
1720 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1721 if (status < 0)
1723 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1724 if (status < 0)
1726 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1727 if (status < 0)
1729 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1730 if (status < 0)
1732 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1733 if (status < 0)
1735 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1736 if (status < 0)
1738 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
1739 if (status < 0)
1744 return status;
1750 int status;
1754 status = -1;
1759 status = 0;
1764 status = -1;
1770 status = WriteTable(state, state->m_InitDiversityFront);
1773 status = WriteTable(state, state->m_InitDiversityEnd);
1779 status = WriteTable(state, state->m_DisableDiversity);
1784 if (!status)
1786 return status;
1792 int status = 0;
1797 status = WriteTable(state, state->m_StartDiversityFront);
1798 if (status < 0)
1801 status = WriteTable(state, state->m_StartDiversityEnd);
1802 if (status < 0)
1805 status = WriteTable(state, state->m_DiversityDelay8MHZ);
1806 if (status < 0)
1809 status = WriteTable(state, state->m_DiversityDelay6MHZ);
1810 if (status < 0)
1814 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
1815 if (status < 0)
1823 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
1824 if (status < 0)
1828 return status;
1873 int status = 0;
1876 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
1877 if (status < 0)
1883 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
1884 if (status < 0)
1887 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
1888 if (status < 0)
1892 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
1893 if (status < 0)
1895 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
1896 if (status < 0)
1901 return status;
1907 int status;
1937 status = ResetECOD(state);
1938 if (status < 0)
1941 status = InitSC(state);
1942 if (status < 0)
1945 status = InitFT(state);
1946 if (status < 0)
1948 status = InitCP(state);
1949 if (status < 0)
1951 status = InitCE(state);
1952 if (status < 0)
1954 status = InitEQ(state);
1955 if (status < 0)
1957 status = InitSC(state);
1958 if (status < 0)
1964 status = SetCfgIfAgc(state, &state->if_agc_cfg);
1965 if (status < 0)
1967 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
1968 if (status < 0)
1980 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
1981 if (status < 0)
1991 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
1992 if (status < 0)
2025 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
2026 if (status < 0)
2028 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
2029 if (status < 0)
2055 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
2056 if (status < 0)
2058 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
2059 if (status < 0)
2084 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
2085 if (status < 0)
2087 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
2088 if (status < 0)
2116 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
2117 if (status < 0)
2119 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
2120 if (status < 0)
2143 status = status;
2144 if (status < 0)
2155 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
2156 if (status < 0)
2158 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
2159 if (status < 0)
2161 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
2162 if (status < 0)
2164 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
2165 if (status < 0)
2167 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
2168 if (status < 0)
2171 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
2172 if (status < 0)
2174 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
2175 if (status < 0)
2177 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
2178 if (status < 0)
2180 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
2181 if (status < 0)
2188 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
2189 if (status < 0)
2191 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
2192 if (status < 0)
2194 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2195 if (status < 0)
2197 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
2198 if (status < 0)
2200 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2201 if (status < 0)
2204 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
2205 if (status < 0)
2207 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
2208 if (status < 0)
2210 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
2211 if (status < 0)
2213 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
2214 if (status < 0)
2222 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
2223 if (status < 0)
2225 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
2226 if (status < 0)
2228 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2229 if (status < 0)
2231 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
2232 if (status < 0)
2234 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2235 if (status < 0)
2238 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
2239 if (status < 0)
2241 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
2242 if (status < 0)
2244 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
2245 if (status < 0)
2247 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
2248 if (status < 0)
2254 status = status;
2255 if (status < 0)
2263 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
2264 if (status < 0)
2269 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
2270 if (status < 0)
2280 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
2281 if (status < 0)
2290 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
2291 if (status < 0)
2298 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
2299 if (status < 0)
2306 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
2307 if (status < 0)
2314 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
2315 if (status < 0)
2320 status = status;
2321 if (status < 0)
2340 status = Write16(state,
2347 status = Write16(state,
2354 status = Write16(state,
2358 status = -EINVAL;
2360 if (status < 0)
2363 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
2364 if (status < 0)
2369 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
2370 if (status < 0)
2383 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
2384 if (status < 0)
2388 status = SetCfgNoiseCalibration(state, &state->noise_cal);
2389 if (status < 0)
2394 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
2395 if (status < 0)
2406 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
2407 if (status < 0)
2409 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
2410 if (status < 0)
2420 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
2421 if (status < 0)
2423 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
2424 if (status < 0)
2435 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
2436 if (status < 0)
2440 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
2441 if (status < 0)
2444 status = StartOC(state);
2445 if (status < 0)
2449 status = StartDiversity(state);
2450 if (status < 0)
2457 return status;
2615 int status = 0;
2626 status = SetDeviceTypeId(state);
2627 if (status < 0)
2632 status = WriteTable(state, state->m_HiI2cPatch);
2633 if (status < 0)
2640 status = Write16(state, 0x43012D, 0x047f, 0);
2641 if (status < 0)
2645 status = HI_ResetCommand(state);
2646 if (status < 0)
2649 status = StopAllProcessors(state);
2650 if (status < 0)
2652 status = InitCC(state);
2653 if (status < 0)
2682 status = InitHI(state);
2683 if (status < 0)
2685 status = InitAtomicRead(state);
2686 if (status < 0)
2689 status = EnableAndResetMB(state);
2690 if (status < 0)
2693 status = ResetCEFR(state);
2694 if (status < 0)
2698 status = DownloadMicrocode(state, fw, fw_size);
2699 if (status < 0)
2702 status = DownloadMicrocode(state, state->microcode, state->microcode_length);
2703 if (status < 0)
2716 status = InitFE(state);
2717 if (status < 0)
2719 status = InitFT(state);
2720 if (status < 0)
2722 status = InitCP(state);
2723 if (status < 0)
2725 status = InitCE(state);
2726 if (status < 0)
2728 status = InitEQ(state);
2729 if (status < 0)
2731 status = InitEC(state);
2732 if (status < 0)
2734 status = InitSC(state);
2735 if (status < 0)
2738 status = SetCfgIfAgc(state, &state->if_agc_cfg);
2739 if (status < 0)
2741 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
2742 if (status < 0)
2746 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2747 if (status < 0)
2749 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2750 if (status < 0)
2761 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
2762 if (status < 0)
2765 status = StopOC(state);
2766 if (status < 0)
2771 status = 0;
2773 return status;
2783 /* Get status again, in case we have MPEG lock now */
2808 static int drxd_read_status(struct dvb_frontend *fe, fe_status_t * status)
2814 *status = 0;
2818 *status |= FE_HAS_LOCK;
2821 *status |= FE_HAS_LOCK;
2824 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
2826 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;