Lines Matching refs:status
255 int status;
266 status = drxk_i2c_transfer(state, &msg, 1);
267 if (status >= 0 && status != 1)
268 status = -EIO;
270 if (status < 0)
273 return status;
279 int status;
287 status = drxk_i2c_transfer(state, msgs, 2);
288 if (status != 2) {
291 if (status >= 0)
292 status = -EIO;
295 return status;
312 int status;
330 status = i2c_read(state, adr, mm1, len, mm2, 2);
331 if (status < 0)
332 return status;
346 int status;
364 status = i2c_read(state, adr, mm1, len, mm2, 4);
365 if (status < 0)
366 return status;
442 int status = 0, blk_size = block_size;
478 status = i2c_write(state, state->demod_address,
480 if (status < 0) {
489 return status;
498 int status;
504 status = i2c_read1(state, state->demod_address, &data);
505 if (status < 0) {
508 status = i2c_write(state, state->demod_address,
512 if (status < 0)
514 status = i2c_read1(state, state->demod_address,
516 } while (status < 0 &&
518 if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)
523 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
524 if (status < 0)
526 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
527 if (status < 0)
530 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
531 if (status < 0)
537 if (status < 0)
538 pr_err("Error %d on %s\n", status, __func__);
540 return status;
781 int status = 0;
788 status = write16(state, SCU_RAM_GPIO__A,
790 if (status < 0)
793 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
794 if (status < 0)
796 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
797 if (status < 0)
799 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
800 if (status < 0)
802 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
803 if (status < 0)
805 status = write16(state, SIO_TOP_COMM_KEY__A, key);
807 if (status < 0)
808 pr_err("Error %d on %s\n", status, __func__);
809 return status;
816 int status;
823 status = write16(state, SCU_RAM_GPIO__A,
825 if (status < 0)
827 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
828 if (status < 0)
830 status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);
831 if (status < 0)
833 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
834 if (status < 0)
861 status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);
862 if (status < 0)
865 pr_info("status = 0x%08x\n", sio_top_jtagid_lo);
883 status = -EINVAL;
995 status = -EINVAL;
1005 if (status < 0)
1006 pr_err("Error %d on %s\n", status, __func__);
1009 return status;
1014 int status;
1020 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1021 if (status < 0)
1039 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1041 } while ((status < 0) && (retry_count < DRXK_MAX_RETRIES)
1043 if (status < 0)
1045 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);
1048 if (status < 0)
1049 pr_err("Error %d on %s\n", status, __func__);
1051 return status;
1056 int status;
1062 status = write16(state, SIO_HI_RA_RAM_PAR_6__A,
1064 if (status < 0)
1066 status = write16(state, SIO_HI_RA_RAM_PAR_5__A,
1068 if (status < 0)
1070 status = write16(state, SIO_HI_RA_RAM_PAR_4__A,
1072 if (status < 0)
1074 status = write16(state, SIO_HI_RA_RAM_PAR_3__A,
1076 if (status < 0)
1078 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
1080 if (status < 0)
1082 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
1084 if (status < 0)
1086 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);
1087 if (status < 0)
1093 if (status < 0)
1094 pr_err("Error %d on %s\n", status, __func__);
1095 return status;
1112 int status = -1;
1122 status = write16(state, SCU_RAM_GPIO__A,
1124 if (status < 0)
1128 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
1129 if (status < 0)
1134 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1135 if (status < 0)
1137 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1138 if (status < 0)
1140 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1141 if (status < 0)
1143 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1144 if (status < 0)
1146 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1147 if (status < 0)
1149 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1150 if (status < 0)
1152 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1153 if (status < 0)
1155 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1156 if (status < 0)
1158 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1159 if (status < 0)
1161 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1162 if (status < 0)
1164 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1165 if (status < 0)
1167 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1168 if (status < 0)
1179 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);
1180 if (status < 0)
1186 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1187 if (status < 0)
1189 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1190 if (status < 0)
1195 status = write16(state, SIO_PDR_MD1_CFG__A,
1197 if (status < 0)
1199 status = write16(state, SIO_PDR_MD2_CFG__A,
1201 if (status < 0)
1203 status = write16(state, SIO_PDR_MD3_CFG__A,
1205 if (status < 0)
1207 status = write16(state, SIO_PDR_MD4_CFG__A,
1209 if (status < 0)
1211 status = write16(state, SIO_PDR_MD5_CFG__A,
1213 if (status < 0)
1215 status = write16(state, SIO_PDR_MD6_CFG__A,
1217 if (status < 0)
1219 status = write16(state, SIO_PDR_MD7_CFG__A,
1221 if (status < 0)
1228 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1229 if (status < 0)
1231 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1232 if (status < 0)
1234 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1235 if (status < 0)
1237 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1238 if (status < 0)
1240 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1241 if (status < 0)
1243 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1244 if (status < 0)
1246 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1247 if (status < 0)
1250 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);
1251 if (status < 0)
1253 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);
1254 if (status < 0)
1258 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1259 if (status < 0)
1262 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1264 if (status < 0)
1265 pr_err("Error %d on %s\n", status, __func__);
1266 return status;
1280 int status;
1285 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1286 if (status < 0)
1288 status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);
1289 if (status < 0)
1291 status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);
1292 if (status < 0)
1294 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1295 if (status < 0)
1301 status = read16(state, SIO_BL_STATUS__A, &bl_status);
1302 if (status < 0)
1309 status = -EINVAL;
1313 if (status < 0)
1314 pr_err("Error %d on %s\n", status, __func__);
1317 return status;
1330 int status = 0;
1374 status = write_block(state, address, block_size, p_src);
1375 if (status < 0) {
1376 pr_err("Error %d while loading firmware\n", status);
1382 return status;
1387 int status;
1400 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1401 if (status >= 0 && data == desired_status) {
1402 /* tokenring already has correct status */
1403 return status;
1406 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);
1410 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1411 if ((status >= 0 && data == desired_status)
1420 return status;
1425 int status = 0;
1432 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1433 if (status < 0)
1436 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1437 if (status < 0)
1441 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);
1442 if (status < 0)
1445 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);
1448 if (status < 0)
1449 pr_err("Error %d on %s\n", status, __func__);
1451 return status;
1462 int status = -EINVAL;
1473 pr_err("Error %d on %s\n", status, __func__);
1474 return status;
1494 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);
1495 if (status < 0)
1500 status = -EIO;
1509 status = read16(state, SCU_RAM_PARAM_0__A - ii,
1511 if (status < 0)
1540 status = -EINVAL;
1545 if (status < 0)
1546 pr_err("Error %d on %s\n", status, __func__);
1549 return status;
1555 int status;
1560 status = read16(state, IQM_AF_STDBY__A, &data);
1561 if (status < 0)
1578 status = write16(state, IQM_AF_STDBY__A, data);
1581 if (status < 0)
1582 pr_err("Error %d on %s\n", status, __func__);
1583 return status;
1588 int status = 0;
1624 status = power_up_device(state);
1625 if (status < 0)
1627 status = dvbt_enable_ofdm_token_ring(state, true);
1628 if (status < 0)
1646 status = mpegts_stop(state);
1647 if (status < 0)
1649 status = power_down_dvbt(state, false);
1650 if (status < 0)
1655 status = mpegts_stop(state);
1656 if (status < 0)
1658 status = power_down_qam(state);
1659 if (status < 0)
1665 status = dvbt_enable_ofdm_token_ring(state, false);
1666 if (status < 0)
1668 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);
1669 if (status < 0)
1671 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1672 if (status < 0)
1678 status = hi_cfg_command(state);
1679 if (status < 0)
1686 if (status < 0)
1687 pr_err("Error %d on %s\n", status, __func__);
1689 return status;
1697 int status;
1701 status = read16(state, SCU_COMM_EXEC__A, &data);
1702 if (status < 0)
1706 status = scu_command(state,
1710 if (status < 0)
1713 status = scu_command(state,
1717 if (status < 0)
1722 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1723 if (status < 0)
1725 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1726 if (status < 0)
1728 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1729 if (status < 0)
1733 status = set_iqm_af(state, false);
1734 if (status < 0)
1739 status = ctrl_power_mode(state, &power_mode);
1740 if (status < 0)
1744 if (status < 0)
1745 pr_err("Error %d on %s\n", status, __func__);
1746 return status;
1752 int status = 0;
1762 status = write16(state, SCU_RAM_GPIO__A,
1764 if (status < 0)
1776 status = mpegts_stop(state);
1777 if (status < 0)
1779 status = power_down_dvbt(state, true);
1780 if (status < 0)
1786 status = mpegts_stop(state);
1787 if (status < 0)
1789 status = power_down_qam(state);
1790 if (status < 0)
1796 status = -EINVAL;
1807 status = set_dvbt_standard(state, o_mode);
1808 if (status < 0)
1816 status = set_qam_standard(state, o_mode);
1817 if (status < 0)
1822 status = -EINVAL;
1825 if (status < 0)
1826 pr_err("Error %d on %s\n", status, __func__);
1827 return status;
1833 int status = -EINVAL;
1854 status = set_qam(state, i_freqk_hz, offsetk_hz);
1855 if (status < 0)
1861 status = mpegts_stop(state);
1862 if (status < 0)
1864 status = set_dvbt(state, i_freqk_hz, offsetk_hz);
1865 if (status < 0)
1867 status = dvbt_start(state);
1868 if (status < 0)
1876 if (status < 0)
1877 pr_err("Error %d on %s\n", status, __func__);
1878 return status;
1891 int status = -EINVAL;
1905 status = get_qam_lock_status(state, p_lock_status);
1908 status = get_dvbt_lock_status(state, p_lock_status);
1914 if (status < 0)
1915 pr_err("Error %d on %s\n", status, __func__);
1916 return status;
1921 int status;
1926 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1927 if (status < 0)
1930 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1931 if (status < 0)
1933 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1935 if (status < 0)
1936 pr_err("Error %d on %s\n", status, __func__);
1937 return status;
1942 int status;
1947 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1948 if (status < 0)
1950 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1951 if (status < 0)
1953 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1954 if (status < 0)
1956 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1957 if (status < 0)
1959 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1960 if (status < 0)
1962 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1963 if (status < 0)
1965 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1966 if (status < 0)
1968 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1969 if (status < 0)
1973 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1974 if (status < 0)
1976 status = write16(state, FEC_OC_SNC_LWM__A, 2);
1977 if (status < 0)
1979 status = write16(state, FEC_OC_SNC_HWM__A, 12);
1981 if (status < 0)
1982 pr_err("Error %d on %s\n", status, __func__);
1984 return status;
1990 int status;
2007 status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);
2008 if (status < 0)
2010 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);
2011 if (status < 0)
2046 status = -EINVAL;
2048 if (status < 0)
2090 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);
2091 if (status < 0)
2093 status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);
2094 if (status < 0)
2096 status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);
2097 if (status < 0)
2099 status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);
2100 if (status < 0)
2102 status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);
2103 if (status < 0)
2105 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);
2106 if (status < 0)
2110 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
2111 if (status < 0)
2113 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,
2115 if (status < 0)
2117 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
2119 if (status < 0)
2120 pr_err("Error %d on %s\n", status, __func__);
2121 return status;
2162 int status = -EINVAL;
2174 status = read16(state, IQM_AF_STDBY__A, &data);
2175 if (status < 0)
2178 status = write16(state, IQM_AF_STDBY__A, data);
2179 if (status < 0)
2181 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2182 if (status < 0)
2193 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2194 if (status < 0)
2198 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2199 if (status < 0)
2207 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2208 if (status < 0)
2218 status = -EINVAL;
2224 status = write16(state,
2227 if (status < 0)
2232 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
2234 if (status < 0)
2238 status = write16(state, SCU_RAM_AGC_RF_MAX__A,
2240 if (status < 0)
2247 status = read16(state, IQM_AF_STDBY__A, &data);
2248 if (status < 0)
2251 status = write16(state, IQM_AF_STDBY__A, data);
2252 if (status < 0)
2256 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2257 if (status < 0)
2264 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2265 if (status < 0)
2269 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2270 if (status < 0)
2274 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,
2276 if (status < 0)
2282 status = read16(state, IQM_AF_STDBY__A, &data);
2283 if (status < 0)
2286 status = write16(state, IQM_AF_STDBY__A, data);
2287 if (status < 0)
2291 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2292 if (status < 0)
2295 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2296 if (status < 0)
2301 status = -EINVAL;
2305 if (status < 0)
2306 pr_err("Error %d on %s\n", status, __func__);
2307 return status;
2316 int status = 0;
2325 status = read16(state, IQM_AF_STDBY__A, &data);
2326 if (status < 0)
2329 status = write16(state, IQM_AF_STDBY__A, data);
2330 if (status < 0)
2333 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2334 if (status < 0)
2345 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2346 if (status < 0)
2350 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2351 if (status < 0)
2358 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2359 if (status < 0)
2369 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2371 if (status < 0)
2378 status = read16(state, IQM_AF_STDBY__A, &data);
2379 if (status < 0)
2382 status = write16(state, IQM_AF_STDBY__A, data);
2383 if (status < 0)
2386 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2387 if (status < 0)
2398 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2399 if (status < 0)
2403 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2405 if (status < 0)
2412 status = read16(state, IQM_AF_STDBY__A, &data);
2413 if (status < 0)
2416 status = write16(state, IQM_AF_STDBY__A, data);
2417 if (status < 0)
2421 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2422 if (status < 0)
2425 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2426 if (status < 0)
2433 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);
2435 if (status < 0)
2436 pr_err("Error %d on %s\n", status, __func__);
2437 return status;
2443 int status = 0;
2455 status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);
2456 if (status < 0) {
2457 pr_err("Error %d on %s\n", status, __func__);
2486 return status;
2492 int status;
2509 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,
2511 if (status < 0)
2513 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,
2515 if (status < 0)
2517 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,
2519 if (status < 0)
2521 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
2523 if (status < 0)
2531 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®_data);
2532 if (status < 0)
2540 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,
2542 if (status < 0)
2588 if (status < 0)
2589 pr_err("Error %d on %s\n", status, __func__);
2590 return status;
2614 int status = 0;
2645 status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2646 if (status < 0)
2648 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2650 if (status < 0)
2654 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2656 if (status < 0)
2680 int status = 0;
2690 status = get_qam_signal_to_noise(state, &signal_to_noise);
2691 if (status < 0)
2722 return status;
2757 int status = -EINVAL;
2769 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
2771 if (status < 0)
2774 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2776 if (status < 0)
2779 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2781 if (status < 0)
2785 status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);
2788 if (status < 0)
2789 pr_err("Error %d on %s\n", status, __func__);
2790 return status;
2796 int status = -EINVAL;
2804 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);
2806 if (status < 0)
2807 pr_err("Error %d on %s\n", status, __func__);
2808 return status;
2817 int status;
2823 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2824 if (status < 0)
2826 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2827 if (status < 0)
2829 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2830 if (status < 0)
2832 status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);
2833 if (status < 0)
2835 status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);
2836 if (status < 0)
2838 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2839 if (status < 0)
2844 status = read16(state, SIO_BL_STATUS__A, &bl_status);
2845 if (status < 0)
2850 status = -EINVAL;
2854 if (status < 0)
2855 pr_err("Error %d on %s\n", status, __func__);
2858 return status;
2865 int status;
2870 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2871 if (status < 0)
2873 status = write16(state, IQM_AF_START_LOCK__A, 1);
2874 if (status < 0)
2878 status = read16(state, IQM_AF_PHASE0__A, &data);
2879 if (status < 0)
2883 status = read16(state, IQM_AF_PHASE1__A, &data);
2884 if (status < 0)
2888 status = read16(state, IQM_AF_PHASE2__A, &data);
2889 if (status < 0)
2895 if (status < 0)
2896 pr_err("Error %d on %s\n", status, __func__);
2897 return status;
2903 int status;
2907 status = adc_sync_measurement(state, &count);
2908 if (status < 0)
2915 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);
2916 if (status < 0)
2928 status = write16(state, IQM_AF_CLKNEG__A, clk_neg);
2929 if (status < 0)
2931 status = adc_sync_measurement(state, &count);
2932 if (status < 0)
2937 status = -EINVAL;
2939 if (status < 0)
2940 pr_err("Error %d on %s\n", status, __func__);
2941 return status;
2954 int status;
3003 status = write32(state, IQM_FS_RATE_OFS_LO__A,
3005 if (status < 0)
3006 pr_err("Error %d on %s\n", status, __func__);
3007 return status;
3029 int status = 0;
3062 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3064 if (status < 0)
3067 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);
3068 if (status < 0)
3070 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);
3071 if (status < 0)
3073 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);
3074 if (status < 0)
3076 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
3077 if (status < 0)
3079 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
3081 if (status < 0)
3083 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
3085 if (status < 0)
3087 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3088 if (status < 0)
3090 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3091 if (status < 0)
3093 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3094 if (status < 0)
3096 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3097 if (status < 0)
3099 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);
3100 if (status < 0)
3102 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);
3103 if (status < 0)
3106 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,
3108 if (status < 0)
3110 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,
3112 if (status < 0)
3114 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
3115 if (status < 0)
3118 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3119 if (status < 0)
3121 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3122 if (status < 0)
3124 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3125 if (status < 0)
3128 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3129 if (status < 0)
3131 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);
3132 if (status < 0)
3134 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);
3135 if (status < 0)
3137 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);
3138 if (status < 0)
3140 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);
3141 if (status < 0)
3143 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3144 if (status < 0)
3146 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3147 if (status < 0)
3149 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3150 if (status < 0)
3152 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3153 if (status < 0)
3155 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3156 if (status < 0)
3158 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3159 if (status < 0)
3161 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3162 if (status < 0)
3164 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3165 if (status < 0)
3167 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3168 if (status < 0)
3170 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3171 if (status < 0)
3173 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3174 if (status < 0)
3176 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3177 if (status < 0)
3179 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3180 if (status < 0)
3182 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3183 if (status < 0)
3187 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3188 if (status < 0)
3197 status = write16(state, SCU_RAM_AGC_KI__A, data);
3199 if (status < 0)
3200 pr_err("Error %d on %s\n", status, __func__);
3201 return status;
3206 int status;
3210 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3212 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,
3214 if (status < 0)
3215 pr_err("Error %d on %s\n", status, __func__);
3216 return status;
3228 int status;
3231 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);
3234 status = -EINVAL;
3236 if (status < 0)
3243 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3246 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3255 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3256 if (status < 0)
3273 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3277 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3282 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3286 status = -EINVAL;
3288 if (status < 0)
3295 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3298 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3302 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);
3305 status = -EINVAL;
3307 if (status < 0)
3319 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3330 status = -EINVAL;
3334 if (status < 0)
3335 pr_err("Error %d on %s\n", status, __func__);
3336 return status;
3342 int status;
3345 status = ctrl_power_mode(state, &power_mode);
3346 if (status < 0)
3347 pr_err("Error %d on %s\n", status, __func__);
3348 return status;
3353 int status;
3357 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3359 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3360 if (status < 0)
3361 pr_err("Error %d on %s\n", status, __func__);
3362 return status;
3369 int status;
3374 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3378 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3380 if (status < 0)
3381 pr_err("Error %d on %s\n", status, __func__);
3383 return status;
3390 int status;
3393 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3394 if (status < 0)
3414 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3416 if (status < 0)
3417 pr_err("Error %d on %s\n", status, __func__);
3418 return status;
3424 int status = -EINVAL;
3436 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3439 if (status < 0)
3440 pr_err("Error %d on %s\n", status, __func__);
3441 return status;
3456 int status;
3464 status = dvbt_ctrl_set_inc_enable(state, &setincenable);
3465 if (status < 0)
3467 status = dvbt_ctrl_set_fr_enable(state, &setfrenable);
3468 if (status < 0)
3470 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);
3471 if (status < 0)
3473 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
3474 if (status < 0)
3476 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
3479 if (status < 0)
3480 pr_err("Error %d on %s\n", status, __func__);
3481 return status;
3499 int status;
3507 status = scu_command(state,
3511 if (status < 0)
3515 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3518 if (status < 0)
3522 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3523 if (status < 0)
3525 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3526 if (status < 0)
3528 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3529 if (status < 0)
3534 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3535 if (status < 0)
3538 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3539 if (status < 0)
3542 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3543 if (status < 0)
3546 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3547 if (status < 0)
3549 status = set_iqm_af(state, true);
3550 if (status < 0)
3553 status = write16(state, IQM_AF_AGC_RF__A, 0);
3554 if (status < 0)
3558 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3559 if (status < 0)
3561 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3562 if (status < 0)
3564 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3565 if (status < 0)
3568 status = write16(state, IQM_RC_STRETCH__A, 16);
3569 if (status < 0)
3571 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3572 if (status < 0)
3574 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3575 if (status < 0)
3577 status = write16(state, IQM_CF_SCALE__A, 1600);
3578 if (status < 0)
3580 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3581 if (status < 0)
3585 status = write16(state, IQM_AF_CLP_TH__A, 448);
3586 if (status < 0)
3588 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3589 if (status < 0)
3592 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,
3594 if (status < 0)
3597 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3598 if (status < 0)
3600 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3601 if (status < 0)
3604 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3605 if (status < 0)
3607 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3608 if (status < 0)
3612 status = adc_synchronization(state);
3613 if (status < 0)
3615 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);
3616 if (status < 0)
3620 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3621 if (status < 0)
3624 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);
3625 if (status < 0)
3627 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);
3628 if (status < 0)
3632 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3633 if (status < 0)
3636 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3637 if (status < 0)
3641 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3642 if (status < 0)
3647 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3649 if (status < 0)
3655 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3656 if (status < 0)
3658 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3659 if (status < 0)
3664 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3665 if (status < 0)
3670 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3671 if (status < 0)
3674 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3675 if (status < 0)
3678 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3679 if (status < 0)
3683 status = mpegts_dto_setup(state, OM_DVBT);
3684 if (status < 0)
3687 status = dvbt_activate_presets(state);
3688 if (status < 0)
3692 if (status < 0)
3693 pr_err("Error %d on %s\n", status, __func__);
3694 return status;
3706 int status;
3713 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,
3716 if (status < 0)
3719 status = mpegts_start(state);
3720 if (status < 0)
3722 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3723 if (status < 0)
3726 if (status < 0)
3727 pr_err("Error %d on %s\n", status, __func__);
3728 return status;
3749 int status;
3754 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3757 if (status < 0)
3761 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3762 if (status < 0)
3766 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3767 if (status < 0)
3769 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3770 if (status < 0)
3775 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3776 if (status < 0)
3868 status = -EINVAL;
3874 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3875 if (status < 0)
3921 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3923 if (status < 0)
3926 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3928 if (status < 0)
3930 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3932 if (status < 0)
3934 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3936 if (status < 0)
3938 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3940 if (status < 0)
3945 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3947 if (status < 0)
3950 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3952 if (status < 0)
3954 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3956 if (status < 0)
3958 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3960 if (status < 0)
3962 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3964 if (status < 0)
3969 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3971 if (status < 0)
3974 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3976 if (status < 0)
3978 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3980 if (status < 0)
3982 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3984 if (status < 0)
3986 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3988 if (status < 0)
3992 status = -EINVAL;
4023 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);
4024 if (status < 0)
4030 status = dvbt_set_frequency_shift(demod, channel, tuner_offset);
4031 if (status < 0)
4034 status = set_frequency_shifter(state, intermediate_freqk_hz,
4036 if (status < 0)
4042 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4043 if (status < 0)
4047 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4048 if (status < 0)
4050 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4051 if (status < 0)
4055 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
4058 if (status < 0)
4067 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4069 if (status < 0)
4073 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);
4075 if (status < 0)
4076 pr_err("Error %d on %s\n", status, __func__);
4078 return status;
4085 * \brief Retrieve lock status .
4087 * \param lockStat Pointer to lock status structure.
4093 int status;
4107 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);
4108 if (status < 0)
4113 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);
4114 if (status < 0)
4126 if (status < 0)
4127 pr_err("Error %d on %s\n", status, __func__);
4129 return status;
4135 int status;
4138 status = ctrl_power_mode(state, &power_mode);
4139 if (status < 0)
4140 pr_err("Error %d on %s\n", status, __func__);
4142 return status;
4151 int status = 0;
4154 status = read16(state, SCU_COMM_EXEC__A, &data);
4155 if (status < 0)
4163 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4164 if (status < 0)
4166 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
4169 if (status < 0)
4173 status = set_iqm_af(state, false);
4176 if (status < 0)
4177 pr_err("Error %d on %s\n", status, __func__);
4179 return status;
4203 int status = 0;
4231 status = -EINVAL;
4233 if (status < 0)
4247 status = -EINVAL;
4248 if (status < 0)
4256 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
4257 if (status < 0)
4259 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,
4261 if (status < 0)
4263 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
4265 if (status < 0)
4266 pr_err("Error %d on %s\n", status, __func__);
4267 return status;
4272 int status = 0;
4277 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4278 if (status < 0)
4280 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4281 if (status < 0)
4283 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4284 if (status < 0)
4286 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4287 if (status < 0)
4289 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4290 if (status < 0)
4292 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4293 if (status < 0)
4296 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4297 if (status < 0)
4299 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4300 if (status < 0)
4302 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4303 if (status < 0)
4305 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4306 if (status < 0)
4308 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4309 if (status < 0)
4311 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4312 if (status < 0)
4315 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4316 if (status < 0)
4318 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4319 if (status < 0)
4321 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4322 if (status < 0)
4326 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4328 if (status < 0)
4332 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4333 if (status < 0)
4335 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4336 if (status < 0)
4338 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4339 if (status < 0)
4341 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4342 if (status < 0)
4344 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4345 if (status < 0)
4347 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4348 if (status < 0)
4350 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4351 if (status < 0)
4353 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4354 if (status < 0)
4357 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4358 if (status < 0)
4360 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4361 if (status < 0)
4363 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4364 if (status < 0)
4366 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4367 if (status < 0)
4369 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4370 if (status < 0)
4372 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4373 if (status < 0)
4375 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4376 if (status < 0)
4378 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4379 if (status < 0)
4381 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4382 if (status < 0)
4384 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4385 if (status < 0)
4387 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4388 if (status < 0)
4390 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4391 if (status < 0)
4397 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4398 if (status < 0)
4400 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4401 if (status < 0)
4403 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4404 if (status < 0)
4406 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4407 if (status < 0)
4409 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4410 if (status < 0)
4412 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4413 if (status < 0)
4416 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4417 if (status < 0)
4419 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4420 if (status < 0)
4422 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4423 if (status < 0)
4429 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4430 if (status < 0)
4432 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4433 if (status < 0)
4435 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4436 if (status < 0)
4438 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4439 if (status < 0)
4441 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4442 if (status < 0)
4444 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4445 if (status < 0)
4447 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4448 if (status < 0)
4452 if (status < 0)
4453 pr_err("Error %d on %s\n", status, __func__);
4454 return status;
4466 int status = 0;
4472 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4473 if (status < 0)
4475 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4476 if (status < 0)
4478 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4479 if (status < 0)
4481 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4482 if (status < 0)
4484 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4485 if (status < 0)
4487 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4488 if (status < 0)
4492 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4493 if (status < 0)
4495 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4496 if (status < 0)
4498 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4499 if (status < 0)
4501 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4502 if (status < 0)
4504 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4505 if (status < 0)
4507 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4508 if (status < 0)
4511 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4512 if (status < 0)
4514 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4515 if (status < 0)
4517 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4518 if (status < 0)
4523 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4525 if (status < 0)
4531 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4532 if (status < 0)
4534 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4535 if (status < 0)
4537 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4538 if (status < 0)
4540 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4541 if (status < 0)
4543 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4544 if (status < 0)
4546 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4547 if (status < 0)
4549 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4550 if (status < 0)
4552 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4553 if (status < 0)
4556 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4557 if (status < 0)
4559 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4560 if (status < 0)
4562 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4563 if (status < 0)
4565 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4566 if (status < 0)
4568 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4569 if (status < 0)
4571 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4572 if (status < 0)
4574 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4575 if (status < 0)
4577 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4578 if (status < 0)
4580 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4581 if (status < 0)
4583 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4584 if (status < 0)
4586 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4587 if (status < 0)
4589 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4590 if (status < 0)
4596 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4597 if (status < 0)
4599 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4600 if (status < 0)
4602 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4603 if (status < 0)
4605 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4606 if (status < 0)
4608 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4609 if (status < 0)
4611 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4612 if (status < 0)
4615 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4616 if (status < 0)
4618 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4619 if (status < 0)
4621 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4622 if (status < 0)
4628 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4629 if (status < 0)
4631 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4632 if (status < 0)
4634 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4635 if (status < 0)
4637 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4638 if (status < 0)
4640 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4641 if (status < 0)
4643 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4644 if (status < 0)
4646 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4648 if (status < 0)
4649 pr_err("Error %d on %s\n", status, __func__);
4650 return status;
4662 int status = 0;
4667 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4668 if (status < 0)
4670 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4671 if (status < 0)
4673 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4674 if (status < 0)
4676 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4677 if (status < 0)
4679 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4680 if (status < 0)
4682 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4683 if (status < 0)
4687 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4688 if (status < 0)
4690 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4691 if (status < 0)
4693 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4694 if (status < 0)
4696 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4697 if (status < 0)
4699 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4700 if (status < 0)
4702 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4703 if (status < 0)
4706 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4707 if (status < 0)
4709 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4710 if (status < 0)
4712 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4713 if (status < 0)
4717 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4719 if (status < 0)
4725 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4726 if (status < 0)
4728 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4729 if (status < 0)
4731 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4732 if (status < 0)
4734 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4735 if (status < 0)
4737 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4738 if (status < 0)
4740 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4741 if (status < 0)
4743 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4744 if (status < 0)
4746 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4747 if (status < 0)
4750 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4751 if (status < 0)
4753 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4754 if (status < 0)
4756 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4757 if (status < 0)
4759 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4760 if (status < 0)
4762 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4763 if (status < 0)
4765 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4766 if (status < 0)
4768 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4769 if (status < 0)
4771 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4772 if (status < 0)
4774 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4775 if (status < 0)
4777 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4778 if (status < 0)
4780 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4781 if (status < 0)
4783 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4784 if (status < 0)
4790 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4791 if (status < 0)
4793 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4794 if (status < 0)
4796 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4797 if (status < 0)
4799 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4800 if (status < 0)
4802 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4803 if (status < 0)
4805 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4806 if (status < 0)
4809 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4810 if (status < 0)
4812 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4813 if (status < 0)
4815 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4816 if (status < 0)
4822 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4823 if (status < 0)
4825 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4826 if (status < 0)
4828 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4829 if (status < 0)
4831 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4832 if (status < 0)
4834 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4835 if (status < 0)
4837 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4838 if (status < 0)
4840 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4842 if (status < 0)
4843 pr_err("Error %d on %s\n", status, __func__);
4845 return status;
4857 int status = 0;
4862 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4863 if (status < 0)
4865 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4866 if (status < 0)
4868 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4869 if (status < 0)
4871 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4872 if (status < 0)
4874 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4875 if (status < 0)
4877 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4878 if (status < 0)
4882 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4883 if (status < 0)
4885 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4886 if (status < 0)
4888 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4889 if (status < 0)
4891 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4892 if (status < 0)
4894 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4895 if (status < 0)
4897 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4898 if (status < 0)
4901 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4902 if (status < 0)
4904 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4905 if (status < 0)
4907 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4908 if (status < 0)
4914 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4916 if (status < 0)
4922 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4923 if (status < 0)
4925 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4926 if (status < 0)
4928 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4929 if (status < 0)
4931 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4932 if (status < 0)
4934 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4935 if (status < 0)
4937 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4938 if (status < 0)
4940 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4941 if (status < 0)
4943 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4944 if (status < 0)
4947 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4948 if (status < 0)
4950 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4951 if (status < 0)
4953 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4954 if (status < 0)
4956 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4957 if (status < 0)
4959 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4960 if (status < 0)
4962 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4963 if (status < 0)
4965 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4966 if (status < 0)
4968 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4969 if (status < 0)
4971 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4972 if (status < 0)
4974 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4975 if (status < 0)
4977 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4978 if (status < 0)
4980 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4981 if (status < 0)
4987 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4988 if (status < 0)
4990 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4991 if (status < 0)
4993 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4994 if (status < 0)
4996 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4997 if (status < 0)
4999 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
5000 if (status < 0)
5002 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
5003 if (status < 0)
5006 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5007 if (status < 0)
5009 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
5010 if (status < 0)
5013 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5014 if (status < 0)
5019 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5020 if (status < 0)
5022 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5023 if (status < 0)
5025 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5026 if (status < 0)
5028 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5029 if (status < 0)
5031 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5032 if (status < 0)
5034 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5035 if (status < 0)
5037 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5039 if (status < 0)
5040 pr_err("Error %d on %s\n", status, __func__);
5042 return status;
5054 int status = 0;
5059 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5060 if (status < 0)
5062 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5063 if (status < 0)
5065 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5066 if (status < 0)
5068 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5069 if (status < 0)
5071 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5072 if (status < 0)
5074 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5075 if (status < 0)
5079 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5080 if (status < 0)
5082 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5083 if (status < 0)
5085 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5086 if (status < 0)
5088 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5089 if (status < 0)
5091 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5092 if (status < 0)
5094 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5095 if (status < 0)
5098 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5099 if (status < 0)
5101 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5102 if (status < 0)
5104 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5105 if (status < 0)
5110 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
5112 if (status < 0)
5118 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5119 if (status < 0)
5121 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5122 if (status < 0)
5124 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5125 if (status < 0)
5127 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5128 if (status < 0)
5130 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5131 if (status < 0)
5133 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5134 if (status < 0)
5136 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5137 if (status < 0)
5139 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5140 if (status < 0)
5143 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5144 if (status < 0)
5146 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5147 if (status < 0)
5149 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5150 if (status < 0)
5152 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5153 if (status < 0)
5155 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5156 if (status < 0)
5158 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5159 if (status < 0)
5161 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5162 if (status < 0)
5164 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5165 if (status < 0)
5167 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5168 if (status < 0)
5170 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5171 if (status < 0)
5173 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5174 if (status < 0)
5176 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5177 if (status < 0)
5183 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5184 if (status < 0)
5186 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5187 if (status < 0)
5189 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5190 if (status < 0)
5192 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5193 if (status < 0)
5195 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5196 if (status < 0)
5198 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5199 if (status < 0)
5202 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5203 if (status < 0)
5205 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5206 if (status < 0)
5208 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5209 if (status < 0)
5215 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5216 if (status < 0)
5218 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5219 if (status < 0)
5221 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5222 if (status < 0)
5224 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5225 if (status < 0)
5227 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5228 if (status < 0)
5230 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5231 if (status < 0)
5233 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5235 if (status < 0)
5236 pr_err("Error %d on %s\n", status, __func__);
5237 return status;
5250 int status;
5255 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5256 if (status < 0)
5259 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5263 if (status < 0)
5264 pr_err("Error %d on %s\n", status, __func__);
5265 return status;
5283 int status;
5296 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5297 if (status < 0)
5306 status = -EINVAL;
5312 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);
5313 if (status < 0)
5322 status = -EINVAL;
5330 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);
5333 if (status < 0)
5334 pr_err("Error %d on %s\n", status, __func__);
5335 return status;
5341 * \brief Get QAM lock status.
5349 int status;
5354 status = scu_command(state,
5358 if (status < 0)
5359 pr_err("Error %d on %s\n", status, __func__);
5378 return status;
5391 int status;
5406 status = scu_command(state,
5410 if (status < 0)
5413 status = scu_command(state,
5429 status = scu_command(state,
5437 status = -EINVAL;
5441 if (status < 0)
5442 pr_warn("Warning %d on %s\n", status, __func__);
5443 return status;
5449 int status;
5460 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5461 if (status < 0)
5463 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5464 if (status < 0)
5466 status = qam_reset_qam(state);
5467 if (status < 0)
5475 status = qam_set_symbolrate(state);
5476 if (status < 0)
5498 status = -EINVAL;
5501 if (status < 0)
5509 status = qam_demodulator_command(state, qam_demod_param_count);
5516 || (!state->qam_demod_parameter_count && status < 0)) {
5518 status = qam_demodulator_command(state, qam_demod_param_count);
5521 if (status < 0) {
5545 status = set_frequency(channel, tuner_freq_offset));
5546 if (status < 0)
5549 status = set_frequency_shifter(state, intermediate_freqk_hz,
5551 if (status < 0)
5555 status = set_qam_measurement(state, state->m_constellation,
5557 if (status < 0)
5561 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5562 if (status < 0)
5564 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5565 if (status < 0)
5569 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5570 if (status < 0)
5572 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5573 if (status < 0)
5575 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5576 if (status < 0)
5578 status = write16(state, QAM_LC_MODE__A, 7);
5579 if (status < 0)
5582 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5583 if (status < 0)
5585 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5586 if (status < 0)
5588 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5589 if (status < 0)
5591 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5592 if (status < 0)
5594 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5595 if (status < 0)
5597 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5598 if (status < 0)
5600 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5601 if (status < 0)
5603 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5604 if (status < 0)
5606 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5607 if (status < 0)
5609 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5610 if (status < 0)
5612 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5613 if (status < 0)
5615 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5616 if (status < 0)
5618 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5619 if (status < 0)
5621 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5622 if (status < 0)
5624 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5625 if (status < 0)
5629 status = write16(state, QAM_SY_SP_INV__A,
5631 if (status < 0)
5635 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5636 if (status < 0)
5642 status = set_qam16(state);
5645 status = set_qam32(state);
5649 status = set_qam64(state);
5652 status = set_qam128(state);
5655 status = set_qam256(state);
5658 status = -EINVAL;
5661 if (status < 0)
5665 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5666 if (status < 0)
5672 status = mpegts_dto_setup(state, state->m_operation_mode);
5673 if (status < 0)
5677 status = mpegts_start(state);
5678 if (status < 0)
5680 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5681 if (status < 0)
5683 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5684 if (status < 0)
5686 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5687 if (status < 0)
5691 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5694 if (status < 0)
5701 if (status < 0)
5702 pr_err("Error %d on %s\n", status, __func__);
5703 return status;
5709 int status;
5722 status = power_up_qam(state);
5723 if (status < 0)
5726 status = qam_reset_qam(state);
5727 if (status < 0)
5732 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5733 if (status < 0)
5735 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5736 if (status < 0)
5743 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
5748 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,
5752 if (status < 0)
5754 status = bl_direct_cmd(state,
5761 status = -EINVAL;
5763 if (status < 0)
5766 status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);
5767 if (status < 0)
5769 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5770 if (status < 0)
5772 status = write16(state, IQM_CF_MIDTAP__A,
5774 if (status < 0)
5777 status = write16(state, IQM_RC_STRETCH__A, 21);
5778 if (status < 0)
5780 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5781 if (status < 0)
5783 status = write16(state, IQM_AF_CLP_TH__A, 448);
5784 if (status < 0)
5786 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5787 if (status < 0)
5789 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5790 if (status < 0)
5793 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5794 if (status < 0)
5796 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5797 if (status < 0)
5799 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5800 if (status < 0)
5802 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5803 if (status < 0)
5807 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5808 if (status < 0)
5810 status = write16(state, IQM_CF_DATATH__A, 1000);
5811 if (status < 0)
5813 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5814 if (status < 0)
5816 status = write16(state, IQM_CF_DET_LCT__A, 0);
5817 if (status < 0)
5819 status = write16(state, IQM_CF_WND_LEN__A, 1);
5820 if (status < 0)
5822 status = write16(state, IQM_CF_PKDTH__A, 1);
5823 if (status < 0)
5825 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5826 if (status < 0)
5830 status = set_iqm_af(state, true);
5831 if (status < 0)
5833 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5834 if (status < 0)
5838 status = adc_synchronization(state);
5839 if (status < 0)
5843 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5844 if (status < 0)
5848 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5849 if (status < 0)
5855 status = init_agc(state, true);
5856 if (status < 0)
5858 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));
5859 if (status < 0)
5863 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);
5864 if (status < 0)
5866 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);
5867 if (status < 0)
5871 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5873 if (status < 0)
5874 pr_err("Error %d on %s\n", status, __func__);
5875 return status;
5880 int status;
5885 status = write16(state, SCU_RAM_GPIO__A,
5887 if (status < 0)
5891 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5892 if (status < 0)
5898 status = write16(state, SIO_PDR_SMA_TX_CFG__A,
5900 if (status < 0)
5904 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5905 if (status < 0)
5912 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5913 if (status < 0)
5918 status = write16(state, SIO_PDR_SMA_RX_CFG__A,
5920 if (status < 0)
5924 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5925 if (status < 0)
5932 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5933 if (status < 0)
5938 status = write16(state, SIO_PDR_GPIO_CFG__A,
5940 if (status < 0)
5944 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5945 if (status < 0)
5952 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5953 if (status < 0)
5958 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5960 if (status < 0)
5961 pr_err("Error %d on %s\n", status, __func__);
5962 return status;
5967 int status = 0;
5983 status = write_gpio(state);
5985 if (status < 0)
5986 pr_err("Error %d on %s\n", status, __func__);
5987 return status;
5992 int status = 0;
6008 status = write_gpio(state);
6010 if (status < 0)
6011 pr_err("Error %d on %s\n", status, __func__);
6012 return status;
6024 int status;
6029 status = ConfigureI2CBridge(state, true);
6030 if (status < 0)
6034 status = dvbt_enable_ofdm_token_ring(state, false);
6035 if (status < 0)
6038 status = write16(state, SIO_CC_PWD_MODE__A,
6040 if (status < 0)
6042 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6043 if (status < 0)
6046 status = hi_cfg_command(state);
6048 if (status < 0)
6049 pr_err("Error %d on %s\n", status, __func__);
6051 return status;
6056 int status = 0, n = 0;
6063 status = power_up_device(state);
6064 if (status < 0)
6066 status = drxx_open(state);
6067 if (status < 0)
6070 status = write16(state, SIO_CC_SOFT_RST__A,
6074 if (status < 0)
6076 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6077 if (status < 0)
6085 status = get_device_capabilities(state);
6086 if (status < 0)
6106 status = init_hi(state);
6107 if (status < 0)
6115 status = write16(state, SCU_RAM_GPIO__A,
6117 if (status < 0)
6122 status = mpegts_disable(state);
6123 if (status < 0)
6127 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6128 if (status < 0)
6130 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6131 if (status < 0)
6135 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6137 if (status < 0)
6141 status = write16(state, SIO_BL_COMM_EXEC__A,
6143 if (status < 0)
6145 status = bl_chain_cmd(state, 0, 6, 100);
6146 if (status < 0)
6150 status = download_microcode(state, state->fw->data,
6152 if (status < 0)
6157 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6159 if (status < 0)
6163 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6164 if (status < 0)
6166 status = drxx_open(state);
6167 if (status < 0)
6173 status = ctrl_power_mode(state, &power_mode);
6174 if (status < 0)
6188 status = write16(state, SCU_RAM_DRIVER_VER_HI__A,
6190 if (status < 0)
6197 status = write16(state, SCU_RAM_DRIVER_VER_LO__A,
6199 if (status < 0)
6217 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6218 if (status < 0)
6223 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6224 if (status < 0)
6227 status = mpegts_dto_init(state);
6228 if (status < 0)
6230 status = mpegts_stop(state);
6231 if (status < 0)
6233 status = mpegts_configure_polarity(state);
6234 if (status < 0)
6236 status = mpegts_configure_pins(state, state->m_enable_mpeg_output);
6237 if (status < 0)
6240 status = write_gpio(state);
6241 if (status < 0)
6247 status = power_down_device(state);
6248 if (status < 0)
6270 if (status < 0) {
6273 pr_err("Error %d on %s\n", status, __func__);
6276 return status;
6420 int status;
6446 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
6447 if (status < 0)
6448 return status;
6452 if (status < 0)
6453 return status;
6479 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
6481 if (status < 0)
6482 return status;
6484 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
6486 if (status < 0)
6487 return status;
6523 int status;
6540 /* get status */
6586 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16);
6587 if (status < 0)
6591 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16);
6592 if (status < 0)
6597 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16);
6598 if (status < 0)
6602 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16);
6603 if (status < 0)
6607 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16);
6608 if (status < 0)
6612 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16);
6613 if (status < 0)
6639 return status;
6643 static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6654 *status = state->fe_status;
6779 int status;
6836 status = request_firmware(&fw, state->microcode_name,
6838 if (status < 0)