Lines Matching defs:state
56 static int itd1000_write_regs(struct itd1000_state *state, u8 reg, u8 v[], u8 len)
60 .addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1
75 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
82 static int itd1000_read_reg(struct itd1000_state *state, u8 reg)
86 { .addr = state->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 },
87 { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = &val, .len = 1 },
91 itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1);
93 if (i2c_transfer(state->i2c, msg, 2) != 2) {
100 static inline int itd1000_write_reg(struct itd1000_state *state, u8 r, u8 v)
102 int ret = itd1000_write_regs(state, r, &v, 1);
103 state->shadow[r] = v;
130 static void itd1000_set_lpf_bw(struct itd1000_state *state, u32 symbol_rate)
133 u8 con1 = itd1000_read_reg(state, CON1) & 0xfd;
134 u8 pllfh = itd1000_read_reg(state, PLLFH) & 0x0f;
135 u8 bbgvmin = itd1000_read_reg(state, BBGVMIN) & 0xf0;
136 u8 bw = itd1000_read_reg(state, BW) & 0xf0;
141 itd1000_write_reg(state, CON1, con1 | (1 << 1));
146 itd1000_write_reg(state, PLLFH, pllfh | (itd1000_lpf_pga[i].pgaext << 4));
147 itd1000_write_reg(state, BBGVMIN, bbgvmin | (itd1000_lpf_pga[i].bbgvmin));
148 itd1000_write_reg(state, BW, bw | (i & 0x0f));
152 itd1000_write_reg(state, CON1, con1 | (0 << 1));
176 static void itd1000_set_vco(struct itd1000_state *state, u32 freq_khz)
179 u8 gvbb_i2c = itd1000_read_reg(state, GVBB_I2C) & 0xbf;
180 u8 vco_chp1_i2c = itd1000_read_reg(state, VCO_CHP1_I2C) & 0x0f;
184 itd1000_write_reg(state, GVBB_I2C, gvbb_i2c | (1 << 6));
188 itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | (itd1000_vcorg[i].vcorg << 4));
191 adcout = itd1000_read_reg(state, PLLLOCK) & 0x0f;
197 itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg + 1) << 4));
200 itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg - 1) << 4));
226 static void itd1000_set_lo(struct itd1000_state *state, u32 freq_khz)
242 state->frequency = ((plln * 1000) + (pllf * 1000)/1048576) * 2*FREF;
243 itd_dbg("frequency: %dkHz (wanted) %dkHz (set), PLLF = %d, PLLN = %d\n", freq_khz, state->frequency, pllf, plln);
245 itd1000_write_reg(state, PLLNH, 0x80); /* PLLNH */
246 itd1000_write_reg(state, PLLNL, plln & 0xff);
247 itd1000_write_reg(state, PLLFH, (itd1000_read_reg(state, PLLFH) & 0xf0) | ((pllf >> 16) & 0x0f));
248 itd1000_write_reg(state, PLLFM, (pllf >> 8) & 0xff);
249 itd1000_write_reg(state, PLLFL, (pllf >> 0) & 0xff);
254 itd1000_write_reg(state, RFTR, itd1000_fre_values[i].values[0]);
256 itd1000_write_reg(state, RFST1+j, itd1000_fre_values[i].values[j+1]);
261 itd1000_set_vco(state, freq_khz);
267 struct itd1000_state *state = fe->tuner_priv;
270 itd1000_set_lo(state, c->frequency);
271 itd1000_set_lpf_bw(state, c->symbol_rate);
273 pllcon1 = itd1000_read_reg(state, PLLCON1) & 0x7f;
274 itd1000_write_reg(state, PLLCON1, pllcon1 | (1 << 7));
275 itd1000_write_reg(state, PLLCON1, pllcon1);
282 struct itd1000_state *state = fe->tuner_priv;
283 *frequency = state->frequency;
334 struct itd1000_state *state = fe->tuner_priv;
338 itd1000_write_reg(state, itd1000_init_tab[i][0], itd1000_init_tab[i][1]);
341 itd1000_write_reg(state, itd1000_reinit_tab[i][0], itd1000_reinit_tab[i][1]);
379 struct itd1000_state *state = NULL;
382 state = kzalloc(sizeof(struct itd1000_state), GFP_KERNEL);
383 if (state == NULL)
386 state->cfg = cfg;
387 state->i2c = i2c;
389 i = itd1000_read_reg(state, 0);
391 kfree(state);
396 memset(state->shadow, 0xff, sizeof(state->shadow));
398 state->shadow[i] = itd1000_read_reg(state, i);
402 fe->tuner_priv = state;