Lines Matching refs:ret

66 	int ret;
79 ret = i2c_transfer(state->i2c, msg, 2);
81 if (ret != 2) {
82 printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret);
100 int ret;
126 ret = i2c_transfer(state->i2c, &msg, 1);
128 if (ret != 1) {
129 dprintk("%s: ret == %d\n", __func__, ret);
161 int ret;
164 ret = mt312_readreg(state, VIT_MODE, &vit_mode);
165 if (ret < 0)
166 return ret;
176 int ret;
183 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h);
184 if (ret < 0)
185 return ret;
189 ret = mt312_writereg(state, MON_CTRL, 0x03);
190 if (ret < 0)
191 return ret;
193 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
194 if (ret < 0)
195 return ret;
202 ret = mt312_writereg(state, MON_CTRL, 0x05);
203 if (ret < 0)
204 return ret;
206 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
207 if (ret < 0)
208 return ret;
212 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf));
213 if (ret < 0)
214 return ret;
234 int ret;
237 ret = mt312_readreg(state, FEC_STATUS, &fec_status);
238 if (ret < 0)
239 return ret;
249 int ret;
253 ret = mt312_writereg(state, CONFIG,
255 if (ret < 0)
256 return ret;
262 ret = mt312_reset(state, 1);
263 if (ret < 0)
264 return ret;
272 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def));
273 if (ret < 0)
274 return ret;
280 ret = mt312_writereg(state, GPP_CTRL, 0x80);
281 if (ret < 0)
282 return ret;
287 ret = mt312_write(state, HW_CTRL, buf, 2);
288 if (ret < 0)
289 return ret;
292 ret = mt312_writereg(state, HW_CTRL, 0x00);
293 if (ret < 0)
294 return ret;
296 ret = mt312_writereg(state, MPEG_CTRL, 0x00);
297 if (ret < 0)
298 return ret;
309 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf));
310 if (ret < 0)
311 return ret;
313 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32);
314 if (ret < 0)
315 return ret;
327 ret = mt312_writereg(state, OP_CTRL, buf[0]);
328 if (ret < 0)
329 return ret;
335 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf));
336 if (ret < 0)
337 return ret;
339 ret = mt312_writereg(state, CS_SW_LIM, 0x69);
340 if (ret < 0)
341 return ret;
350 int ret;
356 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
357 if (ret < 0)
358 return ret;
360 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len);
361 if (ret < 0)
362 return ret;
364 ret = mt312_writereg(state, DISEQC_MODE,
367 if (ret < 0)
368 return ret;
375 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40));
376 if (ret < 0)
377 return ret;
388 int ret;
394 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
395 if (ret < 0)
396 return ret;
398 ret = mt312_writereg(state, DISEQC_MODE,
400 if (ret < 0)
401 return ret;
411 int ret;
417 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
418 if (ret < 0)
419 return ret;
421 ret = mt312_writereg(state, DISEQC_MODE,
423 if (ret < 0)
424 return ret;
448 int ret;
453 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status));
454 if (ret < 0)
455 return ret;
477 int ret;
480 ret = mt312_read(state, RS_BERCNT_H, buf, 3);
481 if (ret < 0)
482 return ret;
493 int ret;
498 ret = mt312_read(state, AGC_H, buf, sizeof(buf));
499 if (ret < 0)
500 return ret;
515 int ret;
518 ret = mt312_read(state, M_SNR_H, buf, sizeof(buf));
519 if (ret < 0)
520 return ret;
530 int ret;
533 ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf));
534 if (ret < 0)
535 return ret;
546 int ret;
582 ret = mt312_readreg(state, CONFIG, &config_val);
583 if (ret < 0)
584 return ret;
590 ret = mt312_initfe(fe);
591 if (ret < 0)
592 return ret;
598 ret = mt312_initfe(fe);
599 if (ret < 0)
600 return ret;
638 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf));
639 if (ret < 0)
640 return ret;
651 int ret;
653 ret = mt312_get_inversion(state, &p->inversion);
654 if (ret < 0)
655 return ret;
657 ret = mt312_get_symbol_rate(state, &p->symbol_rate);
658 if (ret < 0)
659 return ret;
661 ret = mt312_get_code_rate(state, &p->fec_inner);
662 if (ret < 0)
663 return ret;
673 int ret;
677 ret = mt312_readreg(state, GPP_CTRL, &val);
678 if (ret < 0)
691 ret = mt312_writereg(state, GPP_CTRL, val);
694 return ret;
700 int ret;
704 ret = mt312_reset(state, 1);
705 if (ret < 0)
706 return ret;
710 ret = mt312_writereg(state, GPP_CTRL, 0x00);
711 if (ret < 0)
712 return ret;
715 ret = mt312_writereg(state, HW_CTRL, 0x0d);
716 if (ret < 0)
717 return ret;
720 ret = mt312_readreg(state, CONFIG, &config);
721 if (ret < 0)
722 return ret;
725 ret = mt312_writereg(state, CONFIG, config & 0x7f);
726 if (ret < 0)
727 return ret;