Cross Reference: /drivers/media/dvb-frontends/s5h1432.c

Lines Matching defs:state
55 static int s5h1432_writereg(struct s5h1432_state *state,
63 	ret = i2c_transfer(state->i2c, &msg, 1);
72 static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg)
83 	ret = i2c_transfer(state->i2c, msg, 2);
99 	struct s5h1432_state *state = fe->demodulator_priv;
104 	reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E);
119 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg);
125 	struct s5h1432_state *state = fe->demodulator_priv;
129 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
130 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
131 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x15);
134 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
135 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
136 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x40);
139 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
140 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
141 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xe0);
144 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
145 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
146 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
149 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
150 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
151 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xED);
154 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0xAA);
155 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0xAA);
156 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEA);
166 			s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4,
168 			s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5,
170 			s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7,
185 	struct s5h1432_state *state = fe->demodulator_priv;
187 	if (p->frequency == state->current_frequency) {
189 		/*state->current_frequency = p->frequency; */
213 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
215 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
237 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
239 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
243 	state->current_frequency = p->frequency;
250 	struct s5h1432_state *state = fe->demodulator_priv;
253 	state->current_frequency = 0;
259 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8);
260 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01);
261 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70);
262 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80);
263 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D);
264 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30);
265 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20);
266 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B);
267 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40);
268 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84);
269 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a);
270 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3);
271 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50);
272 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c);
273 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10);
274 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c);
275 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00);
276 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94);
277 	/* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1); */
278 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00);
283 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
284 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
285 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
287 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31);
290 	reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42);
292 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg);
297 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
299 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
340 	struct s5h1432_state *state = fe->demodulator_priv;
341 	kfree(state);
349 	struct s5h1432_state *state = NULL;
352 	/* allocate memory for the internal state */
353 	state = kmalloc(sizeof(struct s5h1432_state), GFP_KERNEL);
354 	if (!state)
357 	/* setup the state */
358 	state->config = config;
359 	state->i2c = i2c;
360 	state->current_modulation = QAM_16;
361 	state->inversion = state->config->inversion;
364 	memcpy(&state->frontend.ops, &s5h1432_ops,
367 	state->frontend.demodulator_priv = state;
369 	return &state->frontend;