Lines Matching refs:pll
2 * drivers/media/i2c/smiapp-pll.c
29 #include "smiapp-pll.h"
66 static void print_pll(struct device *dev, struct smiapp_pll *pll)
68 dev_dbg(dev, "pre_pll_clk_div\t%d\n", pll->pre_pll_clk_div);
69 dev_dbg(dev, "pll_multiplier \t%d\n", pll->pll_multiplier);
70 if (pll->flags != SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
71 dev_dbg(dev, "op_sys_clk_div \t%d\n", pll->op_sys_clk_div);
72 dev_dbg(dev, "op_pix_clk_div \t%d\n", pll->op_pix_clk_div);
74 dev_dbg(dev, "vt_sys_clk_div \t%d\n", pll->vt_sys_clk_div);
75 dev_dbg(dev, "vt_pix_clk_div \t%d\n", pll->vt_pix_clk_div);
77 dev_dbg(dev, "ext_clk_freq_hz \t%d\n", pll->ext_clk_freq_hz);
78 dev_dbg(dev, "pll_ip_clk_freq_hz \t%d\n", pll->pll_ip_clk_freq_hz);
79 dev_dbg(dev, "pll_op_clk_freq_hz \t%d\n", pll->pll_op_clk_freq_hz);
80 if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
82 pll->op_sys_clk_freq_hz);
84 pll->op_pix_clk_freq_hz);
86 dev_dbg(dev, "vt_sys_clk_freq_hz \t%d\n", pll->vt_sys_clk_freq_hz);
87 dev_dbg(dev, "vt_pix_clk_freq_hz \t%d\n", pll->vt_pix_clk_freq_hz);
103 struct smiapp_pll *pll, uint32_t mul,
126 dev_dbg(dev, "pre_pll_clk_div %d\n", pll->pre_pll_clk_div);
128 /* Don't go above max pll multiplier. */
132 /* Don't go above max pll op frequency. */
137 / (pll->ext_clk_freq_hz / pll->pre_pll_clk_div * mul));
142 limits->op.max_sys_clk_div * pll->pre_pll_clk_div
154 pll->ext_clk_freq_hz / pll->pre_pll_clk_div
170 more_mul_factor = lcm(div, pll->pre_pll_clk_div) / div;
185 pll->pll_multiplier = mul * i;
186 pll->op_sys_clk_div = div * i / pll->pre_pll_clk_div;
187 dev_dbg(dev, "op_sys_clk_div: %d\n", pll->op_sys_clk_div);
189 pll->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz
190 / pll->pre_pll_clk_div;
192 pll->pll_op_clk_freq_hz = pll->pll_ip_clk_freq_hz
193 * pll->pll_multiplier;
196 pll->op_sys_clk_freq_hz =
197 pll->pll_op_clk_freq_hz / pll->op_sys_clk_div;
199 pll->op_pix_clk_div = pll->bits_per_pixel;
200 dev_dbg(dev, "op_pix_clk_div: %d\n", pll->op_pix_clk_div);
202 pll->op_pix_clk_freq_hz =
203 pll->op_sys_clk_freq_hz / pll->op_pix_clk_div;
213 / pll->binning_horizontal)
214 vt_op_binning_div = pll->binning_horizontal;
230 dev_dbg(dev, "scale_m: %d\n", pll->scale_m);
231 min_vt_div = DIV_ROUND_UP(pll->op_pix_clk_div * pll->op_sys_clk_div
232 * pll->scale_n,
234 * pll->scale_m);
239 DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
251 DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
267 pll->pll_op_clk_freq_hz
280 DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
315 pll->vt_sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div);
316 pll->vt_pix_clk_div = best_pix_div;
318 pll->vt_sys_clk_freq_hz =
319 pll->pll_op_clk_freq_hz / pll->vt_sys_clk_div;
320 pll->vt_pix_clk_freq_hz =
321 pll->vt_sys_clk_freq_hz / pll->vt_pix_clk_div;
323 pll->pixel_rate_csi =
324 pll->op_pix_clk_freq_hz * lane_op_clock_ratio;
326 rval = bounds_check(dev, pll->pll_ip_clk_freq_hz,
332 dev, pll->pll_multiplier,
337 dev, pll->pll_op_clk_freq_hz,
342 dev, pll->op_sys_clk_div,
347 dev, pll->op_pix_clk_div,
352 dev, pll->op_sys_clk_freq_hz,
358 dev, pll->op_pix_clk_freq_hz,
364 dev, pll->vt_sys_clk_freq_hz,
370 dev, pll->vt_pix_clk_freq_hz,
380 struct smiapp_pll *pll)
389 if (pll->flags & SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE)
390 lane_op_clock_ratio = pll->csi2.lanes;
395 dev_dbg(dev, "binning: %dx%d\n", pll->binning_horizontal,
396 pll->binning_vertical);
398 switch (pll->bus_type) {
401 pll->pll_op_clk_freq_hz = pll->link_freq * 2
402 * (pll->csi2.lanes / lane_op_clock_ratio);
405 pll->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel
406 / DIV_ROUND_UP(pll->bits_per_pixel,
407 pll->parallel.bus_width);
413 /* Figure out limits for pre-pll divider based on extclk */
418 clk_div_even(pll->ext_clk_freq_hz /
423 DIV_ROUND_UP(pll->ext_clk_freq_hz,
425 dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %d / %d\n",
428 i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
429 mul = div_u64(pll->pll_op_clk_freq_hz, i);
430 div = pll->ext_clk_freq_hz / i;
436 DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
441 for (pll->pre_pll_clk_div = min_pre_pll_clk_div;
442 pll->pre_pll_clk_div <= max_pre_pll_clk_div;
443 pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) {
444 rval = __smiapp_pll_calculate(dev, limits, pll, mul, div,
449 print_pll(dev, pll);