Cross Reference: /drivers/media/pci/meye/meye.c

Lines Matching refs:mchip_set
448 static inline void mchip_set(int reg, u32 v)
473 	mchip_set(MCHIP_MCC_R_SAMPLING, meye.params.subsample);
474 	mchip_set(MCHIP_MCC_R_XRANGE, mchip_hsize());
475 	mchip_set(MCHIP_MCC_R_YRANGE, mchip_vsize());
476 	mchip_set(MCHIP_MCC_B_XRANGE, mchip_hsize());
477 	mchip_set(MCHIP_MCC_B_YRANGE, mchip_vsize());
484 	mchip_set(MCHIP_HIC_S_RATE, meye.params.framerate);
507 	mchip_set(MCHIP_VRJ_BUS_MODE, 5);
508 	mchip_set(MCHIP_VRJ_SIGNAL_ACTIVE_LEVEL, 0x1f);
509 	mchip_set(MCHIP_VRJ_PDAT_USE, 1);
510 	mchip_set(MCHIP_VRJ_IRQ_FLAG, 0xa0);
511 	mchip_set(MCHIP_VRJ_MODE_SPECIFY, mode);
512 	mchip_set(MCHIP_VRJ_NUM_LINES, mchip_vsize());
513 	mchip_set(MCHIP_VRJ_NUM_PIXELS, mchip_hsize());
514 	mchip_set(MCHIP_VRJ_NUM_COMPONENTS, 0x1b);
515 	mchip_set(MCHIP_VRJ_LIMIT_COMPRESSED_LO, 0xFFFF);
516 	mchip_set(MCHIP_VRJ_LIMIT_COMPRESSED_HI, 0xFFFF);
517 	mchip_set(MCHIP_VRJ_COMP_DATA_FORMAT, 0xC);
518 	mchip_set(MCHIP_VRJ_RESTART_INTERVAL, 0);
519 	mchip_set(MCHIP_VRJ_SOF1, 0x601);
520 	mchip_set(MCHIP_VRJ_SOF2, 0x1502);
521 	mchip_set(MCHIP_VRJ_SOF3, 0x1503);
522 	mchip_set(MCHIP_VRJ_SOF4, 0x1596);
523 	mchip_set(MCHIP_VRJ_SOS, 0x0ed0);
533 	mchip_set(MCHIP_MM_PT_ADDR, (u32)dma_addr);
535 		mchip_set(MCHIP_MM_FIR(i), 0);
567 		mchip_set(MCHIP_HIC_CMD, MCHIP_HIC_CMD_STOP);
577 		mchip_set(MCHIP_HIC_CTL, MCHIP_HIC_CTL_SOFT_RESET);
599 	mchip_set(MCHIP_MM_FIR(meye.mchip_fnum), 0);
669 	mchip_set(MCHIP_HIC_MODE, MCHIP_HIC_MODE_STILL_CAP);
670 	mchip_set(MCHIP_HIC_CMD, MCHIP_HIC_CMD_START);
687 	mchip_set(MCHIP_HIC_MODE, MCHIP_HIC_MODE_STILL_OUT);
688 	mchip_set(MCHIP_HIC_CMD, MCHIP_HIC_CMD_START);
716 	mchip_set(MCHIP_HIC_MODE, MCHIP_HIC_MODE_CONT_OUT);
717 	mchip_set(MCHIP_HIC_CMD, MCHIP_HIC_CMD_START);
731 	mchip_set(MCHIP_HIC_MODE, MCHIP_HIC_MODE_STILL_COMP);
732 	mchip_set(MCHIP_HIC_CMD, MCHIP_HIC_CMD_START);
759 	mchip_set(MCHIP_HIC_MODE, MCHIP_HIC_MODE_STILL_DECOMP);
760 	mchip_set(MCHIP_HIC_CMD, MCHIP_HIC_CMD_START);
779 	mchip_set(MCHIP_HIC_MODE, MCHIP_HIC_MODE_CONT_COMP);
780 	mchip_set(MCHIP_HIC_CMD, MCHIP_HIC_CMD_START);
1565 	mchip_set(MCHIP_MM_INTA, 0x0);
1577 	mchip_set(MCHIP_VRJ_SOFT_RESET, 1);
1579 	mchip_set(MCHIP_MM_PCI_MODE, 5);
1581 	mchip_set(MCHIP_MM_INTA, MCHIP_MM_INTA_HIC_1_MASK);
1716 	mchip_set(MCHIP_VRJ_SOFT_RESET, 1);
1719 	mchip_set(MCHIP_MM_PCI_MODE, 5);
1722 	mchip_set(MCHIP_MM_INTA, MCHIP_MM_INTA_HIC_1_MASK);
1797 	mchip_set(MCHIP_MM_INTA, 0x0);