Lines Matching refs:val
156 static inline void regw(u32 val, u32 offset)
158 __raw_writel(val, isif_cfg.base_addr + offset);
162 static inline u32 reg_modify(u32 mask, u32 val, u32 offset)
164 u32 new_val = (regr(offset) & ~mask) | (val & mask);
170 static inline void regw_lin_tbl(u32 val, u32 offset, int i)
173 __raw_writel(val, isif_cfg.linear_tbl0_addr + offset);
175 __raw_writel(val, isif_cfg.linear_tbl1_addr + offset);
212 u32 val;
215 val = (cul->hcpat_even << CULL_PAT_EVEN_LINE_SHIFT) | cul->hcpat_odd;
216 regw(val, CULH);
230 u32 val;
232 val = (!!gain_off_p->gain_sdram_en << GAIN_SDRAM_EN_SHIFT) |
239 reg_modify(GAIN_OFFSET_EN_MASK, val, CGAMMAWD);
241 val = (gain_off_p->gain.r_ye.integer << GAIN_INTEGER_SHIFT) |
243 regw(val, CRGAIN);
245 val = (gain_off_p->gain.gr_cy.integer << GAIN_INTEGER_SHIFT) |
247 regw(val, CGRGAIN);
249 val = (gain_off_p->gain.gb_g.integer << GAIN_INTEGER_SHIFT) |
251 regw(val, CGBGAIN);
253 val = (gain_off_p->gain.b_mg.integer << GAIN_INTEGER_SHIFT) |
255 regw(val, CBGAIN);
326 u32 val;
335 val = bc->bc_mode_color << ISIF_BC_MODE_COLOR_SHIFT;
338 val = val | 1 | (bc->horz.mode << ISIF_HORZ_BC_MODE_SHIFT);
340 regw(val, CLAMPCFG);
352 val = bc->horz.win_count_calc |
361 regw(val, CLHWIN0);
370 val |=
373 regw(val, CLVWIN0);
388 u32 val, i;
396 val = (linearize->corr_shft << ISIF_LIN_CORRSFT_SHIFT) | 1;
397 regw(val, LINCFG0);
400 val = ((!!linearize->scale_fact.integer) <<
403 regw(val, LINCFG1);
416 u32 val, count, retries = loops_per_jiffy / (4000/HZ);
423 val = (vdfc->corr_mode << ISIF_VDFC_CORR_MOD_SHIFT);
427 val |= 1 << ISIF_VDFC_CORR_WHOLE_LN_SHIFT;
430 val |= vdfc->def_level_shift << ISIF_VDFC_LEVEL_SHFT_SHIFT;
432 regw(val, DFCCTL);
447 val = regr(DFCMEMCTL) | (1 << ISIF_DFCMEMCTL_DFCMARST_SHIFT) | 1;
448 regw(val, DFCMEMCTL);
468 val = regr(DFCMEMCTL);
470 val &= ~BIT(ISIF_DFCMEMCTL_DFCMARST_SHIFT);
471 val |= 1;
472 regw(val, DFCMEMCTL);
550 u32 val;
564 val = ISIF_YCINSWP_RAW | ISIF_CCDCFG_FIDMD_LATCH_VSYNC |
568 dev_dbg(isif_cfg.dev, "Writing 0x%x to ...CCDCFG \n", val);
569 regw(val, CCDCFG);
582 val = ISIF_VDHDOUT_INPUT | (params->vd_pol << ISIF_VD_POL_SHIFT) |
591 regw(val, MODESET);
592 dev_dbg(isif_cfg.dev, "Writing 0x%x to MODESET...\n", val);
598 val = params->cfa_pat << ISIF_GAMMAWD_CFA_SHIFT;
602 val |= ISIF_ALAW_ENABLE;
604 val |= (params->data_msb << ISIF_ALAW_GAMMA_WD_SHIFT);
605 regw(val, CGAMMAWD);
609 val = BIT(ISIF_DPCM_EN_SHIFT) |
614 regw(val, MISC);
620 val = (params->config_params.col_pat_field0.olop) |
628 regw(val, CCOLP);
629 dev_dbg(isif_cfg.dev, "Writing %x to CCOLP ...\n", val);
632 val = (!!params->horz_flip_en) << ISIF_HSIZE_FLIP_SHIFT;
636 val |= ((params->win.width + 31) >> 5);
638 val |= (((params->win.width +
641 val |= (((params->win.width * 2) + 31) >> 5);
642 regw(val, HSIZE);