Lines Matching refs:dev
27 int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev)
32 dev->fw_size = dev->variant->buf_size->fw;
34 if (dev->fw_virt_addr) {
39 dev->fw_virt_addr = dma_alloc_coherent(dev->mem_dev_l, dev->fw_size,
40 &dev->bank1, GFP_KERNEL);
42 if (!dev->fw_virt_addr) {
47 if (HAS_PORTNUM(dev) && IS_TWOPORT(dev)) {
48 bank2_virt = dma_alloc_coherent(dev->mem_dev_r, 1 << MFC_BASE_ALIGN_ORDER,
53 dma_free_coherent(dev->mem_dev_l, dev->fw_size,
54 dev->fw_virt_addr, dev->bank1);
55 dev->fw_virt_addr = NULL;
63 dev->bank2 = bank2_dma_addr - (1 << MFC_BASE_ALIGN_ORDER);
65 dma_free_coherent(dev->mem_dev_r, 1 << MFC_BASE_ALIGN_ORDER,
72 dev->bank2 = dev->bank1;
78 int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev)
88 if (!dev->variant->fw_name[i])
91 dev->variant->fw_name[i], dev->v4l2_dev.dev);
93 dev->fw_ver = (enum s5p_mfc_fw_ver) i;
102 if (fw_blob->size > dev->fw_size) {
107 if (!dev->fw_virt_addr) {
112 memcpy(dev->fw_virt_addr, fw_blob->data, fw_blob->size);
120 int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev)
124 if (!dev->fw_virt_addr)
126 dma_free_coherent(dev->mem_dev_l, dev->fw_size, dev->fw_virt_addr,
127 dev->bank1);
128 dev->fw_virt_addr = NULL;
133 int s5p_mfc_reset(struct s5p_mfc_dev *dev)
141 if (IS_MFCV6_PLUS(dev)) {
144 mfc_write(dev, 0xFEE, S5P_FIMV_MFC_RESET_V6);
146 mfc_write(dev, 0x0, S5P_FIMV_MFC_RESET_V6);
149 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);
150 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6);
151 mfc_write(dev, 0, S5P_FIMV_FW_VERSION_V6);
154 mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4));
157 mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6);
158 mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6);
159 mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6);
163 mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET);
165 mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET);
176 mc_status = mfc_read(dev, S5P_FIMV_MC_STATUS);
180 mfc_write(dev, 0x0, S5P_FIMV_SW_RESET);
181 mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET);
188 static inline void s5p_mfc_init_memctrl(struct s5p_mfc_dev *dev)
190 if (IS_MFCV6_PLUS(dev)) {
191 mfc_write(dev, dev->bank1, S5P_FIMV_RISC_BASE_ADDRESS_V6);
192 mfc_debug(2, "Base Address : %pad\n", &dev->bank1);
194 mfc_write(dev, dev->bank1, S5P_FIMV_MC_DRAMBASE_ADR_A);
195 mfc_write(dev, dev->bank2, S5P_FIMV_MC_DRAMBASE_ADR_B);
197 &dev->bank1, &dev->bank2);
201 static inline void s5p_mfc_clear_cmds(struct s5p_mfc_dev *dev)
203 if (IS_MFCV6_PLUS(dev)) {
207 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH0_INST_ID);
208 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH1_INST_ID);
209 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
210 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD);
215 int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
221 if (!dev->fw_virt_addr) {
229 ret = s5p_mfc_reset(dev);
236 s5p_mfc_init_memctrl(dev);
238 s5p_mfc_clear_cmds(dev);
240 s5p_mfc_clean_dev_int_flags(dev);
241 if (IS_MFCV6_PLUS(dev))
242 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
244 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
246 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
248 s5p_mfc_reset(dev);
252 s5p_mfc_clean_dev_int_flags(dev);
254 ret = s5p_mfc_hw_call(dev->mfc_cmds, sys_init_cmd, dev);
257 s5p_mfc_reset(dev);
262 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SYS_INIT_RET)) {
264 s5p_mfc_reset(dev);
268 dev->int_cond = 0;
269 if (dev->int_err != 0 || dev->int_type !=
273 dev->int_err, dev->int_type);
274 s5p_mfc_reset(dev);
278 if (IS_MFCV6_PLUS(dev))
279 ver = mfc_read(dev, S5P_FIMV_FW_VERSION_V6);
281 ver = mfc_read(dev, S5P_FIMV_FW_VERSION);
292 void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev)
296 s5p_mfc_reset(dev);
297 s5p_mfc_hw_call_void(dev->mfc_ops, release_dev_context_buffer, dev);
302 int s5p_mfc_sleep(struct s5p_mfc_dev *dev)
308 s5p_mfc_clean_dev_int_flags(dev);
309 ret = s5p_mfc_hw_call(dev->mfc_cmds, sleep_cmd, dev);
314 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SLEEP_RET)) {
319 dev->int_cond = 0;
320 if (dev->int_err != 0 || dev->int_type !=
323 mfc_err("Failed to sleep - error: %d int: %d\n", dev->int_err,
324 dev->int_type);
331 int s5p_mfc_wakeup(struct s5p_mfc_dev *dev)
339 ret = s5p_mfc_reset(dev);
346 s5p_mfc_init_memctrl(dev);
348 s5p_mfc_clear_cmds(dev);
349 s5p_mfc_clean_dev_int_flags(dev);
351 ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev);
357 if (IS_MFCV6_PLUS(dev))
358 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
360 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
362 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) {
367 dev->int_cond = 0;
368 if (dev->int_err != 0 || dev->int_type !=
371 mfc_err("Failed to wakeup - error: %d int: %d\n", dev->int_err,
372 dev->int_type);
379 int s5p_mfc_open_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
383 ret = s5p_mfc_hw_call(dev->mfc_ops, alloc_instance_buffer, ctx);
390 ret = s5p_mfc_hw_call(dev->mfc_ops,
400 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
414 s5p_mfc_hw_call_void(dev->mfc_ops, release_dec_desc_buffer, ctx);
416 s5p_mfc_hw_call_void(dev->mfc_ops, release_instance_buffer, ctx);
421 void s5p_mfc_close_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
426 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
433 s5p_mfc_hw_call_void(dev->mfc_ops, release_codec_buffers, ctx);
434 s5p_mfc_hw_call_void(dev->mfc_ops, release_instance_buffer, ctx);
436 s5p_mfc_hw_call_void(dev->mfc_ops, release_dec_desc_buffer, ctx);