Lines Matching refs:mfc_write
144 mfc_write(dev, 0xFEE, S5P_FIMV_MFC_RESET_V6);
146 mfc_write(dev, 0x0, S5P_FIMV_MFC_RESET_V6);
149 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);
150 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6);
151 mfc_write(dev, 0, S5P_FIMV_FW_VERSION_V6);
154 mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4));
157 mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6);
158 mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6);
159 mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6);
163 mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET);
165 mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET);
180 mfc_write(dev, 0x0, S5P_FIMV_SW_RESET);
181 mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET);
191 mfc_write(dev, dev->bank1, S5P_FIMV_RISC_BASE_ADDRESS_V6);
194 mfc_write(dev, dev->bank1, S5P_FIMV_MC_DRAMBASE_ADR_A);
195 mfc_write(dev, dev->bank2, S5P_FIMV_MC_DRAMBASE_ADR_B);
207 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH0_INST_ID);
208 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH1_INST_ID);
209 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
210 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD);
242 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
244 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
358 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
360 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);