Lines Matching refs:dev
50 static void ene_set_reg_addr(struct ene_device *dev, u16 reg)
52 outb(reg >> 8, dev->hw_io + ENE_ADDR_HI);
53 outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO);
57 static u8 ene_read_reg(struct ene_device *dev, u16 reg)
60 ene_set_reg_addr(dev, reg);
61 retval = inb(dev->hw_io + ENE_IO);
67 static void ene_write_reg(struct ene_device *dev, u16 reg, u8 value)
70 ene_set_reg_addr(dev, reg);
71 outb(value, dev->hw_io + ENE_IO);
75 static void ene_set_reg_mask(struct ene_device *dev, u16 reg, u8 mask)
78 ene_set_reg_addr(dev, reg);
79 outb(inb(dev->hw_io + ENE_IO) | mask, dev->hw_io + ENE_IO);
83 static void ene_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask)
86 ene_set_reg_addr(dev, reg);
87 outb(inb(dev->hw_io + ENE_IO) & ~mask, dev->hw_io + ENE_IO);
91 static void ene_set_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask,
95 ene_set_reg_mask(dev, reg, mask);
97 ene_clear_reg_mask(dev, reg, mask);
101 static int ene_hw_detect(struct ene_device *dev)
107 ene_clear_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD);
108 chip_major = ene_read_reg(dev, ENE_ECVER_MAJOR);
109 chip_minor = ene_read_reg(dev, ENE_ECVER_MINOR);
110 ene_set_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD);
112 hw_revision = ene_read_reg(dev, ENE_ECHV);
113 old_ver = ene_read_reg(dev, ENE_HW_VER_OLD);
115 dev->pll_freq = (ene_read_reg(dev, ENE_PLLFRH) << 4) +
116 (ene_read_reg(dev, ENE_PLLFRL) >> 4);
119 dev->rx_period_adjust =
120 dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 2 : 4;
132 pr_notice("PLL freq = %d\n", dev->pll_freq);
140 dev->hw_revision = ENE_HW_C;
143 dev->hw_revision = ENE_HW_B;
146 dev->hw_revision = ENE_HW_D;
151 if (dev->hw_revision < ENE_HW_C)
154 fw_reg1 = ene_read_reg(dev, ENE_FW1);
155 fw_reg2 = ene_read_reg(dev, ENE_FW2);
159 dev->hw_use_gpio_0a = !!(fw_reg2 & ENE_FW2_GP0A);
160 dev->hw_learning_and_tx_capable = !!(fw_reg2 & ENE_FW2_LEARNING);
161 dev->hw_extra_buffer = !!(fw_reg1 & ENE_FW1_HAS_EXTRA_BUF);
163 if (dev->hw_learning_and_tx_capable)
164 dev->hw_fan_input = !!(fw_reg2 & ENE_FW2_FAN_INPUT);
168 if (dev->hw_learning_and_tx_capable) {
177 dev->hw_use_gpio_0a ? "40" : "0A");
179 if (dev->hw_fan_input)
183 if (!dev->hw_fan_input)
185 dev->hw_use_gpio_0a ? "0A" : "40");
187 if (dev->hw_extra_buffer)
193 static void ene_rx_setup_hw_buffer(struct ene_device *dev)
197 ene_rx_read_hw_pointer(dev);
198 dev->r_pointer = dev->w_pointer;
200 if (!dev->hw_extra_buffer) {
201 dev->buffer_len = ENE_FW_PACKET_SIZE * 2;
205 tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER);
206 tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER+1) << 8;
207 dev->extra_buf1_address = tmp;
209 dev->extra_buf1_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 2);
211 tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 3);
212 tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 4) << 8;
213 dev->extra_buf2_address = tmp;
215 dev->extra_buf2_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 5);
217 dev->buffer_len = dev->extra_buf1_len + dev->extra_buf2_len + 8;
221 dev->extra_buf1_address, dev->extra_buf1_len);
223 dev->extra_buf2_address, dev->extra_buf2_len);
225 pr_notice("Total buffer len = %d\n", dev->buffer_len);
227 if (dev->buffer_len > 64 || dev->buffer_len < 16)
230 if (dev->extra_buf1_address > 0xFBFC ||
231 dev->extra_buf1_address < 0xEC00)
234 if (dev->extra_buf2_address > 0xFBFC ||
235 dev->extra_buf2_address < 0xEC00)
238 if (dev->r_pointer > dev->buffer_len)
241 ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
245 dev->hw_extra_buffer = false;
246 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
251 static void ene_rx_restore_hw_buffer(struct ene_device *dev)
253 if (!dev->hw_extra_buffer)
256 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 0,
257 dev->extra_buf1_address & 0xFF);
258 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 1,
259 dev->extra_buf1_address >> 8);
260 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 2, dev->extra_buf1_len);
262 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 3,
263 dev->extra_buf2_address & 0xFF);
264 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 4,
265 dev->extra_buf2_address >> 8);
266 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 5,
267 dev->extra_buf2_len);
268 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
272 static void ene_rx_read_hw_pointer(struct ene_device *dev)
274 if (dev->hw_extra_buffer)
275 dev->w_pointer = ene_read_reg(dev, ENE_FW_RX_POINTER);
277 dev->w_pointer = ene_read_reg(dev, ENE_FW2)
281 dev->w_pointer, dev->r_pointer);
285 static int ene_rx_get_sample_reg(struct ene_device *dev)
289 if (dev->r_pointer == dev->w_pointer) {
291 ene_rx_read_hw_pointer(dev);
294 if (dev->r_pointer == dev->w_pointer) {
295 dbg_verbose("RB: end of data at %d", dev->r_pointer);
299 dbg_verbose("RB: reading at offset %d", dev->r_pointer);
300 r_pointer = dev->r_pointer;
302 dev->r_pointer++;
303 if (dev->r_pointer == dev->buffer_len)
304 dev->r_pointer = 0;
306 dbg_verbose("RB: next read will be from offset %d", dev->r_pointer);
315 if (r_pointer < dev->extra_buf1_len) {
317 return dev->extra_buf1_address + r_pointer;
320 r_pointer -= dev->extra_buf1_len;
322 if (r_pointer < dev->extra_buf2_len) {
324 return dev->extra_buf2_address + r_pointer;
332 static void ene_rx_sense_carrier(struct ene_device *dev)
337 int period = ene_read_reg(dev, ENE_CIRCAR_PRD);
338 int hperiod = ene_read_reg(dev, ENE_CIRCAR_HPRD);
355 if (dev->carrier_detect_enabled) {
359 ir_raw_event_store(dev->rdev, &ev);
364 static void ene_rx_enable_cir_engine(struct ene_device *dev, bool enable)
366 ene_set_clear_reg_mask(dev, ENE_CIRCFG,
371 static void ene_rx_select_input(struct ene_device *dev, bool gpio_0a)
373 ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_GPIO0A, gpio_0a);
380 static void ene_rx_enable_fan_input(struct ene_device *dev, bool enable)
382 if (!dev->hw_fan_input)
386 ene_write_reg(dev, ENE_FAN_AS_IN1, 0);
388 ene_write_reg(dev, ENE_FAN_AS_IN1, ENE_FAN_AS_IN1_EN);
389 ene_write_reg(dev, ENE_FAN_AS_IN2, ENE_FAN_AS_IN2_EN);
394 static void ene_rx_setup(struct ene_device *dev)
396 bool learning_mode = dev->learning_mode_enabled ||
397 dev->carrier_detect_enabled;
404 ene_write_reg(dev, ENE_CIRCFG2, 0x00);
409 dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 1 : 2;
411 ene_write_reg(dev, ENE_CIRRLC_CFG,
415 if (dev->hw_revision < ENE_HW_C)
420 WARN_ON(!dev->hw_learning_and_tx_capable);
427 ene_rx_select_input(dev, !dev->hw_use_gpio_0a);
428 dev->rx_fan_input_inuse = false;
431 ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD);
434 ene_write_reg(dev, ENE_CIRCAR_PULS, 0x63);
435 ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT,
436 dev->carrier_detect_enabled || debug);
438 if (dev->hw_fan_input)
439 dev->rx_fan_input_inuse = true;
441 ene_rx_select_input(dev, dev->hw_use_gpio_0a);
444 ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD);
445 ene_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT);
449 if (dev->rx_fan_input_inuse) {
450 dev->rdev->rx_resolution = US_TO_NS(ENE_FW_SAMPLE_PERIOD_FAN);
454 dev->rdev->min_timeout = dev->rdev->max_timeout =
458 dev->rdev->rx_resolution = US_TO_NS(sample_period);
465 dev->rdev->min_timeout = US_TO_NS(127 * sample_period);
466 dev->rdev->max_timeout = US_TO_NS(200000);
469 if (dev->hw_learning_and_tx_capable)
470 dev->rdev->tx_resolution = US_TO_NS(sample_period);
472 if (dev->rdev->timeout > dev->rdev->max_timeout)
473 dev->rdev->timeout = dev->rdev->max_timeout;
474 if (dev->rdev->timeout < dev->rdev->min_timeout)
475 dev->rdev->timeout = dev->rdev->min_timeout;
479 static void ene_rx_enable_hw(struct ene_device *dev)
484 if (dev->hw_revision < ENE_HW_C) {
485 ene_write_reg(dev, ENEB_IRQ, dev->irq << 1);
486 ene_write_reg(dev, ENEB_IRQ_UNK1, 0x01);
488 reg_value = ene_read_reg(dev, ENE_IRQ) & 0xF0;
491 reg_value |= (dev->irq & ENE_IRQ_MASK);
492 ene_write_reg(dev, ENE_IRQ, reg_value);
496 ene_rx_enable_fan_input(dev, dev->rx_fan_input_inuse);
497 ene_rx_enable_cir_engine(dev, !dev->rx_fan_input_inuse);
500 ene_irq_status(dev);
503 ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ);
506 ir_raw_event_set_idle(dev->rdev, true);
510 static void ene_rx_enable(struct ene_device *dev)
512 ene_rx_enable_hw(dev);
513 dev->rx_enabled = true;
517 static void ene_rx_disable_hw(struct ene_device *dev)
520 ene_rx_enable_cir_engine(dev, false);
521 ene_rx_enable_fan_input(dev, false);
524 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ);
525 ir_raw_event_set_idle(dev->rdev, true);
529 static void ene_rx_disable(struct ene_device *dev)
531 ene_rx_disable_hw(dev);
532 dev->rx_enabled = false;
538 static void ene_rx_reset(struct ene_device *dev)
540 ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN);
541 ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN);
545 static void ene_tx_set_carrier(struct ene_device *dev)
550 spin_lock_irqsave(&dev->hw_lock, flags);
552 ene_set_clear_reg_mask(dev, ENE_CIRCFG,
553 ENE_CIRCFG_TX_CARR, dev->tx_period > 0);
555 if (!dev->tx_period)
558 BUG_ON(dev->tx_duty_cycle >= 100 || dev->tx_duty_cycle <= 0);
560 tx_puls_width = dev->tx_period / (100 / dev->tx_duty_cycle);
565 dbg("TX: pulse distance = %d * 500 ns", dev->tx_period);
568 ene_write_reg(dev, ENE_CIRMOD_PRD, dev->tx_period | ENE_CIRMOD_PRD_POL);
569 ene_write_reg(dev, ENE_CIRMOD_HPRD, tx_puls_width);
571 spin_unlock_irqrestore(&dev->hw_lock, flags);
575 static void ene_tx_set_transmitters(struct ene_device *dev)
579 spin_lock_irqsave(&dev->hw_lock, flags);
580 ene_set_clear_reg_mask(dev, ENE_GPIOFS8, ENE_GPIOFS8_GPIO41,
581 !!(dev->transmitter_mask & 0x01));
582 ene_set_clear_reg_mask(dev, ENE_GPIOFS1, ENE_GPIOFS1_GPIO0D,
583 !!(dev->transmitter_mask & 0x02));
584 spin_unlock_irqrestore(&dev->hw_lock, flags);
588 static void ene_tx_enable(struct ene_device *dev)
590 u8 conf1 = ene_read_reg(dev, ENE_CIRCFG);
591 u8 fwreg2 = ene_read_reg(dev, ENE_FW2);
593 dev->saved_conf1 = conf1;
606 if (dev->hw_revision == ENE_HW_C)
611 ene_write_reg(dev, ENE_CIRCFG, conf1);
615 static void ene_tx_disable(struct ene_device *dev)
617 ene_write_reg(dev, ENE_CIRCFG, dev->saved_conf1);
618 dev->tx_buffer = NULL;
622 /* TX one sample - must be called with dev->hw_lock*/
623 static void ene_tx_sample(struct ene_device *dev)
627 bool pulse = dev->tx_sample_pulse;
629 if (!dev->tx_buffer) {
635 if (!dev->tx_sample) {
637 if (dev->tx_pos == dev->tx_len) {
638 if (!dev->tx_done) {
640 dev->tx_done = true;
644 ene_tx_disable(dev);
645 complete(&dev->tx_complete);
650 sample = dev->tx_buffer[dev->tx_pos++];
651 dev->tx_sample_pulse = !dev->tx_sample_pulse;
653 dev->tx_sample = DIV_ROUND_CLOSEST(sample, sample_period);
655 if (!dev->tx_sample)
656 dev->tx_sample = 1;
659 raw_tx = min(dev->tx_sample , (unsigned int)ENE_CIRRLC_OUT_MASK);
660 dev->tx_sample -= raw_tx;
667 ene_write_reg(dev,
668 dev->tx_reg ? ENE_CIRRLC_OUT1 : ENE_CIRRLC_OUT0, raw_tx);
670 dev->tx_reg = !dev->tx_reg;
674 mod_timer(&dev->tx_sim_timer, jiffies + HZ / 500);
680 struct ene_device *dev = (struct ene_device *)data;
683 spin_lock_irqsave(&dev->hw_lock, flags);
684 ene_tx_sample(dev);
685 spin_unlock_irqrestore(&dev->hw_lock, flags);
690 static int ene_irq_status(struct ene_device *dev)
696 fw_flags2 = ene_read_reg(dev, ENE_FW2);
698 if (dev->hw_revision < ENE_HW_C) {
699 irq_status = ene_read_reg(dev, ENEB_IRQ_STATUS);
704 ene_clear_reg_mask(dev, ENEB_IRQ_STATUS, ENEB_IRQ_STATUS_IR);
708 irq_status = ene_read_reg(dev, ENE_IRQ);
713 ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
714 ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
719 ene_write_reg(dev, ENE_FW2, fw_flags2 & ~ENE_FW2_RXIRQ);
723 fw_flags1 = ene_read_reg(dev, ENE_FW1);
725 ene_write_reg(dev, ENE_FW1, fw_flags1 & ~ENE_FW1_TXIRQ);
740 struct ene_device *dev = (struct ene_device *)data;
743 spin_lock_irqsave(&dev->hw_lock, flags);
746 ene_rx_read_hw_pointer(dev);
747 irq_status = ene_irq_status(dev);
756 if (!dev->hw_learning_and_tx_capable) {
760 ene_tx_sample(dev);
768 if (dev->hw_learning_and_tx_capable)
769 ene_rx_sense_carrier(dev);
773 if (!dev->hw_extra_buffer)
774 dev->r_pointer = dev->w_pointer == 0 ? ENE_FW_PACKET_SIZE : 0;
778 reg = ene_rx_get_sample_reg(dev);
784 hw_value = ene_read_reg(dev, reg);
786 if (dev->rx_fan_input_inuse) {
791 hw_value |= ene_read_reg(dev, reg + offset) << 8;
803 if (dev->rx_period_adjust) {
805 hw_sample /= (100 + dev->rx_period_adjust);
809 if (!dev->hw_extra_buffer && !hw_sample) {
810 dev->r_pointer = dev->w_pointer;
818 ir_raw_event_store_with_filter(dev->rdev, &ev);
821 ir_raw_event_handle(dev->rdev);
823 spin_unlock_irqrestore(&dev->hw_lock, flags);
828 static void ene_setup_default_settings(struct ene_device *dev)
830 dev->tx_period = 32;
831 dev->tx_duty_cycle = 50; /*%*/
832 dev->transmitter_mask = 0x03;
833 dev->learning_mode_enabled = learning_mode_force;
836 dev->rdev->timeout = US_TO_NS(150000);
840 static void ene_setup_hw_settings(struct ene_device *dev)
842 if (dev->hw_learning_and_tx_capable) {
843 ene_tx_set_carrier(dev);
844 ene_tx_set_transmitters(dev);
847 ene_rx_setup(dev);
853 struct ene_device *dev = rdev->priv;
856 spin_lock_irqsave(&dev->hw_lock, flags);
857 ene_rx_enable(dev);
858 spin_unlock_irqrestore(&dev->hw_lock, flags);
865 struct ene_device *dev = rdev->priv;
867 spin_lock_irqsave(&dev->hw_lock, flags);
869 ene_rx_disable(dev);
870 spin_unlock_irqrestore(&dev->hw_lock, flags);
876 struct ene_device *dev = rdev->priv;
886 dev->transmitter_mask = tx_mask;
887 ene_tx_set_transmitters(dev);
894 struct ene_device *dev = rdev->priv;
910 dev->tx_period = period;
911 ene_tx_set_carrier(dev);
918 struct ene_device *dev = rdev->priv;
920 dev->tx_duty_cycle = duty_cycle;
921 ene_tx_set_carrier(dev);
928 struct ene_device *dev = rdev->priv;
930 if (enable == dev->learning_mode_enabled)
933 spin_lock_irqsave(&dev->hw_lock, flags);
934 dev->learning_mode_enabled = enable;
935 ene_rx_disable(dev);
936 ene_rx_setup(dev);
937 ene_rx_enable(dev);
938 spin_unlock_irqrestore(&dev->hw_lock, flags);
944 struct ene_device *dev = rdev->priv;
947 if (enable == dev->carrier_detect_enabled)
950 spin_lock_irqsave(&dev->hw_lock, flags);
951 dev->carrier_detect_enabled = enable;
952 ene_rx_disable(dev);
953 ene_rx_setup(dev);
954 ene_rx_enable(dev);
955 spin_unlock_irqrestore(&dev->hw_lock, flags);
962 struct ene_device *dev = rdev->priv;
965 ene_rx_reset(dev);
973 struct ene_device *dev = rdev->priv;
976 dev->tx_buffer = buf;
977 dev->tx_len = n;
978 dev->tx_pos = 0;
979 dev->tx_reg = 0;
980 dev->tx_done = 0;
981 dev->tx_sample = 0;
982 dev->tx_sample_pulse = false;
984 dbg("TX: %d samples", dev->tx_len);
986 spin_lock_irqsave(&dev->hw_lock, flags);
988 ene_tx_enable(dev);
991 ene_tx_sample(dev);
992 ene_tx_sample(dev);
994 spin_unlock_irqrestore(&dev->hw_lock, flags);
996 if (wait_for_completion_timeout(&dev->tx_complete, 2 * HZ) == 0) {
998 spin_lock_irqsave(&dev->hw_lock, flags);
999 ene_tx_disable(dev);
1000 spin_unlock_irqrestore(&dev->hw_lock, flags);
1011 struct ene_device *dev;
1014 dev = kzalloc(sizeof(struct ene_device), GFP_KERNEL);
1016 if (!dev || !rdev)
1023 dev->hw_io = -1;
1024 dev->irq = -1;
1033 spin_lock_init(&dev->hw_lock);
1035 dev->hw_io = pnp_port_start(pnp_dev, 0);
1036 dev->irq = pnp_irq(pnp_dev, 0);
1039 pnp_set_drvdata(pnp_dev, dev);
1040 dev->pnp_dev = pnp_dev;
1047 error = ene_hw_detect(dev);
1051 if (!dev->hw_learning_and_tx_capable && txsim) {
1052 dev->hw_learning_and_tx_capable = true;
1053 setup_timer(&dev->tx_sim_timer, ene_tx_irqsim,
1054 (long unsigned int)dev);
1058 if (!dev->hw_learning_and_tx_capable)
1063 rdev->priv = dev;
1071 if (dev->hw_learning_and_tx_capable) {
1073 init_completion(&dev->tx_complete);
1082 dev->rdev = rdev;
1084 ene_rx_setup_hw_buffer(dev);
1085 ene_setup_default_settings(dev);
1086 ene_setup_hw_settings(dev);
1088 device_set_wakeup_capable(&pnp_dev->dev, true);
1089 device_set_wakeup_enable(&pnp_dev->dev, true);
1097 if (!request_region(dev->hw_io, ENE_IO_SIZE, ENE_DRIVER_NAME)) {
1101 if (request_irq(dev->irq, ene_isr,
1102 IRQF_SHARED, ENE_DRIVER_NAME, (void *)dev)) {
1110 release_region(dev->hw_io, ENE_IO_SIZE);
1116 kfree(dev);
1123 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1126 spin_lock_irqsave(&dev->hw_lock, flags);
1127 ene_rx_disable(dev);
1128 ene_rx_restore_hw_buffer(dev);
1129 spin_unlock_irqrestore(&dev->hw_lock, flags);
1131 free_irq(dev->irq, dev);
1132 release_region(dev->hw_io, ENE_IO_SIZE);
1133 rc_unregister_device(dev->rdev);
1134 kfree(dev);
1138 static void ene_enable_wake(struct ene_device *dev, bool enable)
1141 ene_set_clear_reg_mask(dev, ENE_FW1, ENE_FW1_WAKE, enable);
1147 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1148 bool wake = device_may_wakeup(&dev->pnp_dev->dev);
1150 if (!wake && dev->rx_enabled)
1151 ene_rx_disable_hw(dev);
1153 ene_enable_wake(dev, wake);
1159 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1160 ene_setup_hw_settings(dev);
1162 if (dev->rx_enabled)
1163 ene_rx_enable(dev);
1165 ene_enable_wake(dev, false);
1172 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1173 ene_enable_wake(dev, true);