Lines Matching defs:nvt
43 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
45 outb(reg, nvt->cr_efir);
46 outb(val, nvt->cr_efdr);
50 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
52 outb(reg, nvt->cr_efir);
53 return inb(nvt->cr_efdr);
57 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
59 u8 tmp = nvt_cr_read(nvt, reg) | val;
60 nvt_cr_write(nvt, tmp, reg);
64 static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
66 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
67 nvt_cr_write(nvt, tmp, reg);
71 static inline void nvt_efm_enable(struct nvt_dev *nvt)
74 outb(EFER_EFM_ENABLE, nvt->cr_efir);
75 outb(EFER_EFM_ENABLE, nvt->cr_efir);
79 static inline void nvt_efm_disable(struct nvt_dev *nvt)
81 outb(EFER_EFM_DISABLE, nvt->cr_efir);
89 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
91 outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir);
92 outb(ldev, nvt->cr_efdr);
96 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
98 outb(val, nvt->cir_addr + offset);
102 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
106 val = inb(nvt->cir_addr + offset);
112 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
115 outb(val, nvt->cir_wake_addr + offset);
119 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
123 val = inb(nvt->cir_wake_addr + offset);
129 static void cir_dump_regs(struct nvt_dev *nvt)
131 nvt_efm_enable(nvt);
132 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
136 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
138 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
139 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
141 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
143 nvt_efm_disable(nvt);
146 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
147 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
148 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
149 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
150 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
151 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
152 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
153 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
154 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
155 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
156 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
157 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
158 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
159 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
160 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
161 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
165 static void cir_wake_dump_regs(struct nvt_dev *nvt)
169 nvt_efm_enable(nvt);
170 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
175 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
177 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
178 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
180 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
182 nvt_efm_disable(nvt);
186 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
188 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
190 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
192 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
194 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
196 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
198 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
200 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
202 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
204 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
206 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
208 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
210 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
212 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
214 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
216 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
218 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
223 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
228 static int nvt_hw_detect(struct nvt_dev *nvt)
235 nvt_efm_enable(nvt);
238 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
240 nvt->cr_efir = CR_EFIR2;
241 nvt->cr_efdr = CR_EFDR2;
242 nvt_efm_enable(nvt);
243 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
246 chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
280 nvt_efm_disable(nvt);
282 spin_lock_irqsave(&nvt->nvt_lock, flags);
283 nvt->chip_major = chip_major;
284 nvt->chip_minor = chip_minor;
285 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
290 static void nvt_cir_ldev_init(struct nvt_dev *nvt)
294 if (nvt->chip_major == CHIP_ID_HIGH_667) {
305 val = nvt_cr_read(nvt, psreg);
308 nvt_cr_write(nvt, val, psreg);
311 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
312 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
314 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
315 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
317 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
320 nvt->cir_addr, nvt->cir_irq);
323 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
326 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
327 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
330 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
333 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
336 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
337 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
339 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
340 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
342 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
345 nvt->cir_wake_addr, nvt->cir_wake_irq);
349 static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
353 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
354 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
358 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
362 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
363 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
368 static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
372 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
373 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
377 static void nvt_set_cir_iren(struct nvt_dev *nvt)
382 nvt_cir_reg_write(nvt, iren, CIR_IREN);
385 static void nvt_cir_regs_init(struct nvt_dev *nvt)
388 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
389 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
392 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
399 nvt_cir_reg_write(nvt,
405 nvt_clear_cir_fifo(nvt);
406 nvt_clear_tx_fifo(nvt);
409 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
412 nvt_set_cir_iren(nvt);
415 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
418 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES,
422 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
426 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
427 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
430 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
437 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
443 nvt_clear_cir_wake_fifo(nvt);
446 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
449 static void nvt_enable_wake(struct nvt_dev *nvt)
451 nvt_efm_enable(nvt);
453 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
454 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
455 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
457 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
458 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
460 nvt_efm_disable(nvt);
462 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
466 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
467 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
472 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
477 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
478 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
480 for (i = 0; i < nvt->pkts; i++) {
481 if (nvt->buf[i] & BUF_PULSE_BIT)
482 duration += nvt->buf[i] & BUF_LEN_MASK;
513 struct nvt_dev *nvt = dev->priv;
519 nvt_cir_reg_write(nvt, 1, CIR_CP);
521 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
524 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
549 struct nvt_dev *nvt = dev->priv;
555 spin_lock_irqsave(&nvt->tx.lock, flags);
558 nvt->tx.buf_count = (ret * sizeof(unsigned));
560 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
562 nvt->tx.cur_buf_num = 0;
565 iren = nvt_cir_reg_read(nvt, CIR_IREN);
568 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
570 nvt->tx.tx_state = ST_TX_REPLY;
572 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
577 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
579 spin_unlock_irqrestore(&nvt->tx.lock, flags);
581 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
583 spin_lock_irqsave(&nvt->tx.lock, flags);
584 nvt->tx.tx_state = ST_TX_NONE;
585 spin_unlock_irqrestore(&nvt->tx.lock, flags);
588 nvt_cir_reg_write(nvt, iren, CIR_IREN);
594 static void nvt_dump_rx_buf(struct nvt_dev *nvt)
598 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
599 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
600 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
616 static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
625 nvt_dump_rx_buf(nvt);
627 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
631 for (i = 0; i < nvt->pkts; i++) {
632 sample = nvt->buf[i];
641 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
648 if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) {
650 ir_raw_event_handle(nvt->rdev);
654 nvt->pkts = 0;
657 ir_raw_event_handle(nvt->rdev);
662 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
666 nvt->pkts = 0;
667 nvt_clear_cir_fifo(nvt);
668 ir_raw_event_reset(nvt->rdev);
672 static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
681 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
693 spin_lock_irqsave(&nvt->nvt_lock, flags);
695 b_idx = nvt->pkts;
699 nvt_process_rx_ir_data(nvt);
705 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
706 nvt->buf[b_idx + i] = val;
709 nvt->pkts += fifocount;
710 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
712 nvt_process_rx_ir_data(nvt);
715 nvt_handle_rx_fifo_overrun(nvt);
717 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
737 static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
743 spin_lock_irqsave(&nvt->tx.lock, flags);
744 tx_state = nvt->tx.tx_state;
745 spin_unlock_irqrestore(&nvt->tx.lock, flags);
755 struct nvt_dev *nvt = data;
761 nvt_efm_enable(nvt);
762 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
763 nvt_efm_disable(nvt);
778 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
781 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
786 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
787 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
790 iren = nvt_cir_reg_read(nvt, CIR_IREN);
802 if (nvt_cir_tx_inactive(nvt))
803 nvt_get_rx_ir_data(nvt);
807 if (nvt_cir_tx_inactive(nvt))
808 nvt_get_rx_ir_data(nvt);
810 spin_lock_irqsave(&nvt->nvt_lock, flags);
812 cur_state = nvt->study_state;
814 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
817 nvt_clear_cir_fifo(nvt);
821 nvt_clear_tx_fifo(nvt);
827 spin_lock_irqsave(&nvt->tx.lock, flags);
829 pos = nvt->tx.cur_buf_num;
830 count = nvt->tx.buf_count;
834 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
835 nvt->tx.cur_buf_num++;
838 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
839 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
842 spin_unlock_irqrestore(&nvt->tx.lock, flags);
847 spin_lock_irqsave(&nvt->tx.lock, flags);
848 if (nvt->tx.tx_state == ST_TX_REPLY) {
849 nvt->tx.tx_state = ST_TX_REQUEST;
850 wake_up(&nvt->tx.queue);
852 spin_unlock_irqrestore(&nvt->tx.lock, flags);
863 struct nvt_dev *nvt = data;
868 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
873 nvt_clear_cir_wake_fifo(nvt);
875 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
876 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
879 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
886 (nvt->wake_state == ST_WAKE_START)) {
887 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
888 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
892 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
893 spin_lock_irqsave(&nvt->nvt_lock, flags);
894 nvt->wake_state = ST_WAKE_FINISH;
895 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
902 static void nvt_enable_cir(struct nvt_dev *nvt)
905 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
909 nvt_efm_enable(nvt);
912 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
913 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
915 nvt_efm_disable(nvt);
918 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
921 nvt_set_cir_iren(nvt);
924 static void nvt_disable_cir(struct nvt_dev *nvt)
927 nvt_cir_reg_write(nvt, 0, CIR_IREN);
930 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
933 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
936 nvt_clear_cir_fifo(nvt);
937 nvt_clear_tx_fifo(nvt);
939 nvt_efm_enable(nvt);
942 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
943 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
945 nvt_efm_disable(nvt);
950 struct nvt_dev *nvt = dev->priv;
953 spin_lock_irqsave(&nvt->nvt_lock, flags);
954 nvt_enable_cir(nvt);
955 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
962 struct nvt_dev *nvt = dev->priv;
965 spin_lock_irqsave(&nvt->nvt_lock, flags);
966 nvt_disable_cir(nvt);
967 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
973 struct nvt_dev *nvt;
977 nvt = kzalloc(sizeof(struct nvt_dev), GFP_KERNEL);
978 if (!nvt)
1011 nvt->cir_addr = pnp_port_start(pdev, 0);
1012 nvt->cir_irq = pnp_irq(pdev, 0);
1014 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1016 nvt->cir_wake_irq = nvt->cir_irq;
1018 nvt->cr_efir = CR_EFIR;
1019 nvt->cr_efdr = CR_EFDR;
1021 spin_lock_init(&nvt->nvt_lock);
1022 spin_lock_init(&nvt->tx.lock);
1024 pnp_set_drvdata(pdev, nvt);
1025 nvt->pdev = pdev;
1027 init_waitqueue_head(&nvt->tx.queue);
1029 ret = nvt_hw_detect(nvt);
1034 nvt_efm_enable(nvt);
1035 nvt_cir_ldev_init(nvt);
1036 nvt_cir_wake_ldev_init(nvt);
1037 nvt_efm_disable(nvt);
1040 nvt_cir_regs_init(nvt);
1041 nvt_cir_wake_regs_init(nvt);
1044 rdev->priv = nvt;
1055 rdev->input_id.product = nvt->chip_major;
1056 rdev->input_id.version = nvt->chip_minor;
1069 nvt->rdev = rdev;
1077 if (!request_region(nvt->cir_addr,
1081 if (request_irq(nvt->cir_irq, nvt_cir_isr, IRQF_SHARED,
1082 NVT_DRIVER_NAME, (void *)nvt))
1085 if (!request_region(nvt->cir_wake_addr,
1089 if (request_irq(nvt->cir_wake_irq, nvt_cir_wake_isr, IRQF_SHARED,
1090 NVT_DRIVER_NAME, (void *)nvt))
1097 cir_dump_regs(nvt);
1098 cir_wake_dump_regs(nvt);
1104 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1106 free_irq(nvt->cir_irq, nvt);
1108 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1114 kfree(nvt);
1121 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1124 spin_lock_irqsave(&nvt->nvt_lock, flags);
1126 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1127 nvt_disable_cir(nvt);
1129 nvt_enable_wake(nvt);
1130 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1133 free_irq(nvt->cir_irq, nvt);
1134 free_irq(nvt->cir_wake_irq, nvt);
1135 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1136 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1138 rc_unregister_device(nvt->rdev);
1140 kfree(nvt);
1145 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1151 spin_lock_irqsave(&nvt->nvt_lock, flags);
1152 nvt->study_state = ST_STUDY_NONE;
1153 nvt->wake_state = ST_WAKE_NONE;
1154 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1156 spin_lock_irqsave(&nvt->tx.lock, flags);
1157 nvt->tx.tx_state = ST_TX_NONE;
1158 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1161 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1163 nvt_efm_enable(nvt);
1166 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1167 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
1169 nvt_efm_disable(nvt);
1172 nvt_enable_wake(nvt);
1179 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1184 nvt_set_cir_iren(nvt);
1187 nvt_efm_enable(nvt);
1188 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1189 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
1191 nvt_efm_disable(nvt);
1193 nvt_cir_regs_init(nvt);
1194 nvt_cir_wake_regs_init(nvt);
1201 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1202 nvt_enable_wake(nvt);