Lines Matching refs:MT2063_REG_VGA_GAIN
204 MT2063_REG_VGA_GAIN, /* 0x30: VGA Gain Ctrl */
1053 if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
1058 if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
1088 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
1089 if (state->reg[MT2063_REG_VGA_GAIN] !=
1093 MT2063_REG_VGA_GAIN,
1114 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
1115 if (state->reg[MT2063_REG_VGA_GAIN] !=
1119 MT2063_REG_VGA_GAIN,
1140 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */
1141 if (state->reg[MT2063_REG_VGA_GAIN] !=
1145 MT2063_REG_VGA_GAIN,
1166 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */
1167 if (state->reg[MT2063_REG_VGA_GAIN] !=
1171 MT2063_REG_VGA_GAIN,