Lines Matching refs:fe
299 static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value);
300 static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value);
301 static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
303 static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum,
306 static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal);
307 static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
309 static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val);
310 static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
312 static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq);
313 static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe);
314 static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe);
315 static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
317 static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
319 static u16 MXL_IFSynthInit(struct dvb_frontend *fe);
320 static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
322 static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
337 static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
339 struct mxl5005s_state *state = fe->tuner_priv;
356 mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
359 MXL_TuneRF(fe, RfFreqHz);
361 MXL_ControlRead(fe, IF_DIVVAL, &IfDivval);
363 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0);
364 MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1);
365 MXL_ControlWrite(fe, IF_DIVVAL, 8);
366 MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen);
374 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
380 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1);
381 MXL_ControlWrite(fe, IF_DIVVAL, IfDivval);
382 MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen);
390 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
402 static u16 MXL5005_RegisterInit(struct dvb_frontend *fe)
404 struct mxl5005s_state *state = fe->tuner_priv;
722 static u16 MXL5005_ControlInit(struct dvb_frontend *fe)
724 struct mxl5005s_state *state = fe->tuner_priv;
1662 static void InitTunerControls(struct dvb_frontend *fe)
1664 MXL5005_RegisterInit(fe);
1665 MXL5005_ControlInit(fe);
1667 MXL5005_MXLControlInit(fe);
1671 static u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
1694 struct mxl5005s_state *state = fe->tuner_priv;
1712 InitTunerControls(fe);
1715 MXL_SynthIFLO_Calc(fe);
1720 static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe)
1722 struct mxl5005s_state *state = fe->tuner_priv;
1733 static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe)
1735 struct mxl5005s_state *state = fe->tuner_priv;
1754 static u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
1758 status += MXL_ControlWrite(fe, OVERRIDE_1, 1);
1759 status += MXL_ControlWrite(fe, OVERRIDE_2, 1);
1760 status += MXL_ControlWrite(fe, OVERRIDE_3, 1);
1761 status += MXL_ControlWrite(fe, OVERRIDE_4, 1);
1766 static u16 MXL_BlockInit(struct dvb_frontend *fe)
1768 struct mxl5005s_state *state = fe->tuner_priv;
1771 status += MXL_OverwriteICDefault(fe);
1774 status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0);
1777 status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1);
1778 status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2);
1779 status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0);
1780 status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1);
1781 status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 0);
1787 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0);
1790 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2);
1793 status += MXL_ControlWrite(fe,
1800 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1804 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1808 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1815 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8);
1816 status += MXL_ControlWrite(fe,
1818 status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0);
1822 status += MXL_ControlWrite(fe, AGC_IF, 15);
1823 status += MXL_ControlWrite(fe, AGC_RF, 15);
1825 status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12);
1828 status += MXL_ControlWrite(fe, AGC_IF, 0x0);
1831 status += MXL_ControlWrite(fe, AGC_IF, 0x1);
1834 status += MXL_ControlWrite(fe, AGC_IF, 0x2);
1837 status += MXL_ControlWrite(fe, AGC_IF, 0x3);
1840 status += MXL_ControlWrite(fe, AGC_IF, 0x4);
1843 status += MXL_ControlWrite(fe, AGC_IF, 0x5);
1846 status += MXL_ControlWrite(fe, AGC_IF, 0x6);
1849 status += MXL_ControlWrite(fe, AGC_IF, 0x7);
1852 status += MXL_ControlWrite(fe, AGC_IF, 0x9);
1855 status += MXL_ControlWrite(fe, AGC_IF, 0xA);
1858 status += MXL_ControlWrite(fe, AGC_IF, 0xB);
1861 status += MXL_ControlWrite(fe, AGC_IF, 0xC);
1864 status += MXL_ControlWrite(fe, AGC_IF, 0xD);
1867 status += MXL_ControlWrite(fe, AGC_IF, 0xE);
1870 status += MXL_ControlWrite(fe, AGC_IF, 0xF);
1873 status += MXL_IFSynthInit(fe);
1877 status += MXL_ControlWrite(fe, DRV_RES_SEL, 6);
1878 status += MXL_ControlWrite(fe, I_DRIVER, 2);
1881 status += MXL_ControlWrite(fe, DRV_RES_SEL, 4);
1882 status += MXL_ControlWrite(fe, I_DRIVER, 1);
1890 status += MXL_ControlWrite(fe, EN_AAF, 1);
1891 status += MXL_ControlWrite(fe, EN_3P, 1);
1892 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1893 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1897 status += MXL_ControlWrite(fe, EN_AAF, 1);
1898 status += MXL_ControlWrite(fe, EN_3P, 1);
1899 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1900 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
1903 status += MXL_ControlWrite(fe, EN_AAF, 0);
1904 status += MXL_ControlWrite(fe, EN_3P, 1);
1905 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1906 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
1910 status += MXL_ControlWrite(fe, EN_AAF, 1);
1911 status += MXL_ControlWrite(fe, EN_3P, 1);
1912 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1913 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1916 status += MXL_ControlWrite(fe, EN_AAF, 0);
1917 status += MXL_ControlWrite(fe, EN_3P, 0);
1918 status += MXL_ControlWrite(fe, EN_AUX_3P, 0);
1919 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1925 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 1);
1927 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 0);
1930 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 1);
1932 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 0);
1936 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 1);
1938 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 0);
1941 status += MXL_ControlWrite(fe, IF_SEL_DBL, 1);
1943 status += MXL_ControlWrite(fe, IF_SEL_DBL, 0);
1946 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 3);
1948 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0);
1952 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0);
1954 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1);
1956 /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */
1959 status += MXL_ControlWrite(fe, TG_R_DIV,
1966 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
1967 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
1968 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
1969 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
1972 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
1973 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 3);
1974 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
1977 status += MXL_ControlWrite(fe, RFA_FLR, 0);
1978 status += MXL_ControlWrite(fe, RFA_CEIL, 12);
1988 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
1989 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
1990 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
1991 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
1994 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
1995 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
1996 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
1999 status += MXL_ControlWrite(fe, RFA_FLR, 2);
2000 status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2002 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2004 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2011 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2012 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2013 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2014 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2017 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
2018 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 4);
2019 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
2022 status += MXL_ControlWrite(fe, RFA_FLR, 2);
2023 status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2024 status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1);
2026 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
2029 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2031 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2039 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2040 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2041 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2042 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2045 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2046 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2047 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2049 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2052 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2054 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2055 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
2065 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2066 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2067 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2068 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2070 status += MXL_ControlWrite(fe, AGC_IF, 1);
2071 status += MXL_ControlWrite(fe, AGC_RF, 15);
2072 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2080 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2081 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2082 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2083 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2086 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2087 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2088 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2089 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2090 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2095 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2096 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2097 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2098 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2104 static u16 MXL_IFSynthInit(struct dvb_frontend *fe)
2106 struct mxl5005s_state *state = fe->tuner_priv;
2121 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2122 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2126 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2127 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2131 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2132 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2136 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2137 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2141 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2142 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2146 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2147 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2151 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2152 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2156 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2157 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2164 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2165 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2169 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2170 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2174 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2175 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2179 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2180 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2184 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2185 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2189 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2190 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2194 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2195 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2199 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2200 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2204 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2205 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2209 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
2210 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2214 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
2215 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2219 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
2220 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2224 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05);
2225 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2229 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2230 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2234 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2235 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2239 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2240 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2244 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2245 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2249 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2250 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2254 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2255 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2259 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2260 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2264 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2265 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2269 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2270 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2274 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
2275 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2279 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
2280 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2284 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
2285 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2289 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05);
2290 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2297 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal);
2303 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal);
2308 static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2310 struct mxl5005s_state *state = fe->tuner_priv;
2323 MXL_SynthRFTGLO_Calc(fe);
2343 status += MXL_ControlWrite(fe, DN_POLY, 2);
2344 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2345 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423);
2346 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2347 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
2350 status += MXL_ControlWrite(fe, DN_POLY, 3);
2351 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2352 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222);
2353 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2354 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
2357 status += MXL_ControlWrite(fe, DN_POLY, 3);
2358 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2359 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147);
2360 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2361 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
2364 status += MXL_ControlWrite(fe, DN_POLY, 3);
2365 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2366 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9);
2367 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2368 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
2371 status += MXL_ControlWrite(fe, DN_POLY, 3);
2372 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2373 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
2374 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2375 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
2378 status += MXL_ControlWrite(fe, DN_POLY, 3);
2379 status += MXL_ControlWrite(fe, DN_RFGAIN, 1);
2380 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
2381 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0);
2382 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
2385 status += MXL_ControlWrite(fe, DN_POLY, 3);
2386 status += MXL_ControlWrite(fe, DN_RFGAIN, 2);
2387 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
2388 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0);
2389 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
2397 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2398 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2401 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2402 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2405 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2406 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2409 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2410 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2413 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2414 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2417 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2418 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2421 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2422 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2425 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2426 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2429 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2430 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2433 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2434 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2437 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2438 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2441 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2442 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2445 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2446 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2449 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2450 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2453 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10);
2454 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1);
2457 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10);
2458 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1);
2477 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2478 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2479 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2480 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2481 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2482 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2490 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2491 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2492 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2493 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2494 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2495 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2503 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2504 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2505 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2506 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2507 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2508 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2516 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2517 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2518 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2519 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2520 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2521 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2529 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2530 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2531 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2532 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2533 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2534 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2);
2542 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2543 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2544 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2545 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2546 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2547 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2);
2555 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2556 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2557 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2558 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2559 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2560 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4);
2568 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2569 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2570 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2571 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2572 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2573 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2581 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2582 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2583 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2584 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2585 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2);
2586 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2594 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2595 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2596 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2597 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1);
2598 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2599 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2607 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2608 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2609 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2610 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1);
2611 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2612 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2625 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3);
2629 MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4);
2636 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
2640 status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A);
2643 status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0));
2645 * status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1);
2647 * status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
2665 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6);
2666 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0);
2674 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1);
2675 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0);
2683 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC);
2684 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
2692 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
2693 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
2701 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
2702 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
2710 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
2711 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3);
2719 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
2720 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3);
2728 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
2729 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7);
2737 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
2738 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7);
2749 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval);
2752 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1);
2785 status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo);
2790 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN,
2793 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2795 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
2801 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2802 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2803 status += MXL_SetGPIO(fe, 3, 1); /* Bank1 Off */
2804 status += MXL_SetGPIO(fe, 1, 1); /* Bank2 Off */
2805 status += MXL_SetGPIO(fe, 4, 1); /* Bank3 Off */
2809 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2810 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2813 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2814 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2815 status += MXL_SetGPIO(fe, 3, 0);
2816 status += MXL_SetGPIO(fe, 1, 1);
2817 status += MXL_SetGPIO(fe, 4, 1);
2820 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2821 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2822 status += MXL_SetGPIO(fe, 3, 1);
2823 status += MXL_SetGPIO(fe, 1, 0);
2824 status += MXL_SetGPIO(fe, 4, 1);
2827 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2828 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2829 status += MXL_SetGPIO(fe, 3, 1);
2830 status += MXL_SetGPIO(fe, 1, 0);
2831 status += MXL_SetGPIO(fe, 4, 0);
2834 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2835 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2836 status += MXL_SetGPIO(fe, 3, 1);
2837 status += MXL_SetGPIO(fe, 1, 1);
2838 status += MXL_SetGPIO(fe, 4, 0);
2841 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2842 status += MXL_ControlWrite(fe, DAC_DIN_B, 29);
2843 status += MXL_SetGPIO(fe, 3, 1);
2844 status += MXL_SetGPIO(fe, 1, 1);
2845 status += MXL_SetGPIO(fe, 4, 0);
2848 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2849 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2850 status += MXL_SetGPIO(fe, 3, 1);
2851 status += MXL_SetGPIO(fe, 1, 1);
2852 status += MXL_SetGPIO(fe, 4, 0);
2855 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2856 status += MXL_ControlWrite(fe, DAC_DIN_B, 16);
2857 status += MXL_SetGPIO(fe, 3, 1);
2858 status += MXL_SetGPIO(fe, 1, 1);
2859 status += MXL_SetGPIO(fe, 4, 1);
2862 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2863 status += MXL_ControlWrite(fe, DAC_DIN_B, 7);
2864 status += MXL_SetGPIO(fe, 3, 1);
2865 status += MXL_SetGPIO(fe, 1, 1);
2866 status += MXL_SetGPIO(fe, 4, 1);
2869 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2870 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2871 status += MXL_SetGPIO(fe, 3, 1);
2872 status += MXL_SetGPIO(fe, 1, 1);
2873 status += MXL_SetGPIO(fe, 4, 1);
2880 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2883 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2884 status += MXL_SetGPIO(fe, 4, 0);
2885 status += MXL_SetGPIO(fe, 3, 1);
2886 status += MXL_SetGPIO(fe, 1, 1);
2889 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2890 status += MXL_SetGPIO(fe, 4, 1);
2891 status += MXL_SetGPIO(fe, 3, 0);
2892 status += MXL_SetGPIO(fe, 1, 1);
2895 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2896 status += MXL_SetGPIO(fe, 4, 1);
2897 status += MXL_SetGPIO(fe, 3, 0);
2898 status += MXL_SetGPIO(fe, 1, 0);
2901 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2902 status += MXL_SetGPIO(fe, 4, 1);
2903 status += MXL_SetGPIO(fe, 3, 1);
2904 status += MXL_SetGPIO(fe, 1, 0);
2907 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2908 status += MXL_SetGPIO(fe, 4, 1);
2909 status += MXL_SetGPIO(fe, 3, 1);
2910 status += MXL_SetGPIO(fe, 1, 0);
2913 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2914 status += MXL_SetGPIO(fe, 4, 1);
2915 status += MXL_SetGPIO(fe, 3, 1);
2916 status += MXL_SetGPIO(fe, 1, 0);
2919 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2920 status += MXL_SetGPIO(fe, 4, 1);
2921 status += MXL_SetGPIO(fe, 3, 1);
2922 status += MXL_SetGPIO(fe, 1, 1);
2925 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2926 status += MXL_SetGPIO(fe, 4, 1);
2927 status += MXL_SetGPIO(fe, 3, 1);
2928 status += MXL_SetGPIO(fe, 1, 1);
2931 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2932 status += MXL_SetGPIO(fe, 4, 1);
2933 status += MXL_SetGPIO(fe, 3, 1);
2934 status += MXL_SetGPIO(fe, 1, 1);
2940 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2943 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2944 status += MXL_SetGPIO(fe, 4, 0);
2945 status += MXL_SetGPIO(fe, 1, 1);
2946 status += MXL_SetGPIO(fe, 3, 1);
2949 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2950 status += MXL_SetGPIO(fe, 4, 0);
2951 status += MXL_SetGPIO(fe, 1, 0);
2952 status += MXL_SetGPIO(fe, 3, 1);
2955 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2956 status += MXL_SetGPIO(fe, 4, 1);
2957 status += MXL_SetGPIO(fe, 1, 0);
2958 status += MXL_SetGPIO(fe, 3, 1);
2961 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2962 status += MXL_SetGPIO(fe, 4, 1);
2963 status += MXL_SetGPIO(fe, 1, 0);
2964 status += MXL_SetGPIO(fe, 3, 0);
2967 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2968 status += MXL_SetGPIO(fe, 4, 1);
2969 status += MXL_SetGPIO(fe, 1, 1);
2970 status += MXL_SetGPIO(fe, 3, 0);
2973 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2974 status += MXL_SetGPIO(fe, 4, 1);
2975 status += MXL_SetGPIO(fe, 1, 1);
2976 status += MXL_SetGPIO(fe, 3, 0);
2979 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2980 status += MXL_SetGPIO(fe, 4, 1);
2981 status += MXL_SetGPIO(fe, 1, 1);
2982 status += MXL_SetGPIO(fe, 3, 1);
2989 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2995 status += MXL_SetGPIO(fe, 3, 1);
2996 status += MXL_SetGPIO(fe, 1, 1);
2997 status += MXL_SetGPIO(fe, 4, 1);
2998 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2999 status += MXL_ControlWrite(fe, AGC_IF, 10);
3005 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3006 status += MXL_SetGPIO(fe, 4, 1);
3007 status += MXL_SetGPIO(fe, 1, 1);
3008 status += MXL_SetGPIO(fe, 3, 0);
3012 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3013 status += MXL_SetGPIO(fe, 4, 1);
3014 status += MXL_SetGPIO(fe, 1, 0);
3015 status += MXL_SetGPIO(fe, 3, 0);
3019 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3020 status += MXL_SetGPIO(fe, 4, 0);
3021 status += MXL_SetGPIO(fe, 1, 1);
3022 status += MXL_SetGPIO(fe, 3, 0);
3026 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3027 status += MXL_SetGPIO(fe, 4, 0);
3028 status += MXL_SetGPIO(fe, 1, 0);
3029 status += MXL_SetGPIO(fe, 3, 1);
3033 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3034 status += MXL_SetGPIO(fe, 4, 1);
3035 status += MXL_SetGPIO(fe, 1, 0);
3036 status += MXL_SetGPIO(fe, 3, 1);
3040 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3041 status += MXL_SetGPIO(fe, 4, 0);
3042 status += MXL_SetGPIO(fe, 1, 0);
3043 status += MXL_SetGPIO(fe, 3, 1);
3047 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3048 status += MXL_SetGPIO(fe, 4, 0);
3049 status += MXL_SetGPIO(fe, 1, 1);
3050 status += MXL_SetGPIO(fe, 3, 1);
3054 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3055 status += MXL_SetGPIO(fe, 4, 0);
3056 status += MXL_SetGPIO(fe, 1, 1);
3057 status += MXL_SetGPIO(fe, 3, 1);
3061 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3062 status += MXL_SetGPIO(fe, 4, 1);
3063 status += MXL_SetGPIO(fe, 1, 1);
3064 status += MXL_SetGPIO(fe, 3, 1);
3071 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3074 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3075 status += MXL_SetGPIO(fe, 4, 0);
3076 status += MXL_SetGPIO(fe, 1, 1);
3077 status += MXL_SetGPIO(fe, 3, 1);
3080 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3081 status += MXL_SetGPIO(fe, 4, 0);
3082 status += MXL_SetGPIO(fe, 1, 0);
3083 status += MXL_SetGPIO(fe, 3, 1);
3086 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3087 status += MXL_SetGPIO(fe, 4, 1);
3088 status += MXL_SetGPIO(fe, 1, 0);
3089 status += MXL_SetGPIO(fe, 3, 1);
3092 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3093 status += MXL_SetGPIO(fe, 4, 1);
3094 status += MXL_SetGPIO(fe, 1, 0);
3095 status += MXL_SetGPIO(fe, 3, 0);
3098 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3099 status += MXL_SetGPIO(fe, 4, 1);
3100 status += MXL_SetGPIO(fe, 1, 1);
3101 status += MXL_SetGPIO(fe, 3, 0);
3104 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3105 status += MXL_SetGPIO(fe, 4, 1);
3106 status += MXL_SetGPIO(fe, 1, 1);
3107 status += MXL_SetGPIO(fe, 3, 0);
3110 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3111 status += MXL_SetGPIO(fe, 4, 1);
3112 status += MXL_SetGPIO(fe, 1, 1);
3113 status += MXL_SetGPIO(fe, 3, 1);
3120 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3123 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3124 status += MXL_SetGPIO(fe, 4, 0);
3125 status += MXL_SetGPIO(fe, 1, 1);
3126 status += MXL_SetGPIO(fe, 3, 1);
3129 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3130 status += MXL_SetGPIO(fe, 4, 0);
3131 status += MXL_SetGPIO(fe, 1, 0);
3132 status += MXL_SetGPIO(fe, 3, 1);
3135 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3136 status += MXL_SetGPIO(fe, 4, 1);
3137 status += MXL_SetGPIO(fe, 1, 0);
3138 status += MXL_SetGPIO(fe, 3, 1);
3141 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3142 status += MXL_SetGPIO(fe, 4, 1);
3143 status += MXL_SetGPIO(fe, 1, 0);
3144 status += MXL_SetGPIO(fe, 3, 0);
3147 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3148 status += MXL_SetGPIO(fe, 4, 1);
3149 status += MXL_SetGPIO(fe, 1, 1);
3150 status += MXL_SetGPIO(fe, 3, 0);
3153 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3154 status += MXL_SetGPIO(fe, 4, 1);
3155 status += MXL_SetGPIO(fe, 1, 1);
3156 status += MXL_SetGPIO(fe, 3, 0);
3159 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3160 status += MXL_SetGPIO(fe, 4, 1);
3161 status += MXL_SetGPIO(fe, 1, 1);
3162 status += MXL_SetGPIO(fe, 3, 1);
3169 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3172 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3173 status += MXL_SetGPIO(fe, 4, 0);
3174 status += MXL_SetGPIO(fe, 1, 1);
3175 status += MXL_SetGPIO(fe, 3, 1);
3178 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3179 status += MXL_SetGPIO(fe, 4, 0);
3180 status += MXL_SetGPIO(fe, 1, 0);
3181 status += MXL_SetGPIO(fe, 3, 1);
3184 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3185 status += MXL_SetGPIO(fe, 4, 1);
3186 status += MXL_SetGPIO(fe, 1, 0);
3187 status += MXL_SetGPIO(fe, 3, 1);
3190 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3191 status += MXL_SetGPIO(fe, 4, 1);
3192 status += MXL_SetGPIO(fe, 1, 0);
3193 status += MXL_SetGPIO(fe, 3, 0);
3196 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3197 status += MXL_SetGPIO(fe, 4, 1);
3198 status += MXL_SetGPIO(fe, 1, 1);
3199 status += MXL_SetGPIO(fe, 3, 0);
3202 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3203 status += MXL_SetGPIO(fe, 4, 1);
3204 status += MXL_SetGPIO(fe, 1, 1);
3205 status += MXL_SetGPIO(fe, 3, 0);
3208 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3209 status += MXL_SetGPIO(fe, 4, 1);
3210 status += MXL_SetGPIO(fe, 1, 1);
3211 status += MXL_SetGPIO(fe, 3, 1);
3218 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3222 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3223 status += MXL_SetGPIO(fe, 4, 0);
3224 status += MXL_SetGPIO(fe, 1, 1);
3225 status += MXL_SetGPIO(fe, 3, 1);
3228 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3229 status += MXL_SetGPIO(fe, 4, 0);
3230 status += MXL_SetGPIO(fe, 1, 0);
3231 status += MXL_SetGPIO(fe, 3, 1);
3234 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3235 status += MXL_SetGPIO(fe, 4, 1);
3236 status += MXL_SetGPIO(fe, 1, 0);
3237 status += MXL_SetGPIO(fe, 3, 1);
3240 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3241 status += MXL_SetGPIO(fe, 4, 1);
3242 status += MXL_SetGPIO(fe, 1, 0);
3243 status += MXL_SetGPIO(fe, 3, 0);
3246 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3247 status += MXL_SetGPIO(fe, 4, 1);
3248 status += MXL_SetGPIO(fe, 1, 0);
3249 status += MXL_SetGPIO(fe, 3, 1);
3252 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3253 status += MXL_SetGPIO(fe, 4, 1);
3254 status += MXL_SetGPIO(fe, 1, 1);
3255 status += MXL_SetGPIO(fe, 3, 0);
3258 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3259 status += MXL_SetGPIO(fe, 4, 1);
3260 status += MXL_SetGPIO(fe, 1, 1);
3261 status += MXL_SetGPIO(fe, 3, 0);
3264 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3265 status += MXL_SetGPIO(fe, 4, 1);
3266 status += MXL_SetGPIO(fe, 1, 1);
3267 status += MXL_SetGPIO(fe, 3, 1);
3274 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3281 status += MXL_SetGPIO(fe, 3, 1);
3282 status += MXL_SetGPIO(fe, 1, 1);
3283 status += MXL_SetGPIO(fe, 4, 1);
3284 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3287 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
3288 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
3289 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
3290 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
3293 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
3294 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
3295 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
3299 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
3304 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
3307 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
3312 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3313 status += MXL_SetGPIO(fe, 4, 0);
3314 status += MXL_SetGPIO(fe, 1, 1);
3315 status += MXL_SetGPIO(fe, 3, 1);
3318 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3319 status += MXL_SetGPIO(fe, 4, 0);
3320 status += MXL_SetGPIO(fe, 1, 0);
3321 status += MXL_SetGPIO(fe, 3, 1);
3324 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3325 status += MXL_SetGPIO(fe, 4, 1);
3326 status += MXL_SetGPIO(fe, 1, 0);
3327 status += MXL_SetGPIO(fe, 3, 1);
3330 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3331 status += MXL_SetGPIO(fe, 4, 1);
3332 status += MXL_SetGPIO(fe, 1, 0);
3333 status += MXL_SetGPIO(fe, 3, 0);
3336 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3337 status += MXL_SetGPIO(fe, 4, 1);
3338 status += MXL_SetGPIO(fe, 1, 1);
3339 status += MXL_SetGPIO(fe, 3, 0);
3342 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3343 status += MXL_SetGPIO(fe, 4, 1);
3344 status += MXL_SetGPIO(fe, 1, 1);
3345 status += MXL_SetGPIO(fe, 3, 0);
3348 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3349 status += MXL_SetGPIO(fe, 4, 1);
3350 status += MXL_SetGPIO(fe, 1, 1);
3351 status += MXL_SetGPIO(fe, 3, 1);
3358 static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val)
3363 status += MXL_ControlWrite(fe, GPIO_1B, GPIO_Val ? 0 : 1);
3369 status += MXL_ControlWrite(fe, GPIO_3, 0);
3370 status += MXL_ControlWrite(fe, GPIO_3B, 0);
3373 status += MXL_ControlWrite(fe, GPIO_3, 1);
3374 status += MXL_ControlWrite(fe, GPIO_3B, 1);
3377 status += MXL_ControlWrite(fe, GPIO_3, 0);
3378 status += MXL_ControlWrite(fe, GPIO_3B, 1);
3383 status += MXL_ControlWrite(fe, GPIO_4, 0);
3384 status += MXL_ControlWrite(fe, GPIO_4B, 0);
3387 status += MXL_ControlWrite(fe, GPIO_4, 1);
3388 status += MXL_ControlWrite(fe, GPIO_4B, 1);
3391 status += MXL_ControlWrite(fe, GPIO_4, 0);
3392 status += MXL_ControlWrite(fe, GPIO_4B, 1);
3399 static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value)
3405 status += MXL_ControlWrite_Group(fe, ControlNum, value, 1);
3407 status += MXL_ControlWrite_Group(fe, ControlNum, value, 2);
3410 status += MXL_ControlWrite_Group(fe, ControlNum, value, 3);
3415 static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
3418 struct mxl5005s_state *state = fe->tuner_priv;
3433 MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]),
3455 MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]),
3478 MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]),
3496 static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
3498 struct mxl5005s_state *state = fe->tuner_priv;
3511 static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
3513 struct mxl5005s_state *state = fe->tuner_priv;
3559 static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
3562 struct mxl5005s_state *state = fe->tuner_priv;
3590 static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
3603 status += MXL_BlockInit(fe);
3607 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3613 static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal,
3637 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3643 static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
3655 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3676 static u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
3678 struct mxl5005s_state *state = fe->tuner_priv;
3682 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3683 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3684 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3685 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3686 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3687 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3688 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3691 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3692 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3693 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3694 status += MXL_ControlWrite(fe,
3699 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3700 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3701 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3702 status += MXL_ControlWrite(fe,
3706 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3707 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3708 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3709 status += MXL_ControlWrite(fe,
3715 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3716 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3717 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3718 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3719 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3720 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3721 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3722 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3723 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3724 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
3727 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3728 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3729 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3730 status += MXL_ControlWrite(fe,
3735 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3736 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3737 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3738 status += MXL_ControlWrite(fe,
3742 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3743 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3744 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
3745 status += MXL_ControlWrite(fe,
3751 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3752 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3753 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3754 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3755 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3756 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3757 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3758 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3759 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3760 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3763 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3764 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3765 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
3766 status += MXL_ControlWrite(fe,
3771 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3772 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3773 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
3774 status += MXL_ControlWrite(fe,
3778 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3779 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3780 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3781 status += MXL_ControlWrite(fe,
3787 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3788 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3789 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3790 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3791 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3792 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3793 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3794 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3795 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3796 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3799 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3800 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3801 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3802 status += MXL_ControlWrite(fe,
3807 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3808 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3809 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3810 status += MXL_ControlWrite(fe,
3814 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3815 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3816 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3817 status += MXL_ControlWrite(fe,
3825 static u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis)
3827 struct mxl5005s_state *state = fe->tuner_priv;
3831 status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1);
3844 static int mxl5005s_reset(struct dvb_frontend *fe)
3846 struct mxl5005s_state *state = fe->tuner_priv;
3855 if (fe->ops.i2c_gate_ctrl)
3856 fe->ops.i2c_gate_ctrl(fe, 1);
3863 if (fe->ops.i2c_gate_ctrl)
3864 fe->ops.i2c_gate_ctrl(fe, 0);
3872 static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch)
3874 struct mxl5005s_state *state = fe->tuner_priv;
3891 static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
3896 if (fe->ops.i2c_gate_ctrl)
3897 fe->ops.i2c_gate_ctrl(fe, 1);
3900 ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0);
3905 ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1);
3907 if (fe->ops.i2c_gate_ctrl)
3908 fe->ops.i2c_gate_ctrl(fe, 0);
3913 static int mxl5005s_init(struct dvb_frontend *fe)
3915 struct mxl5005s_state *state = fe->tuner_priv;
3919 return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ);
3922 static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
3925 struct mxl5005s_state *state = fe->tuner_priv;
3933 mxl5005s_reset(fe);
3940 mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
3942 mxl5005s_AssignTunerMode(fe, mod_type, bandwidth);
3945 MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen);
3947 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
3952 static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
3955 struct mxl5005s_state *state = fe->tuner_priv;
3958 InitTunerControls(fe);
3962 fe,
3981 static int mxl5005s_set_params(struct dvb_frontend *fe)
3983 struct mxl5005s_state *state = fe->tuner_priv;
3984 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
4023 ret = mxl5005s_reconfigure(fe, req_mode, req_bw);
4030 ret = mxl5005s_SetRfFreqHz(fe, c->frequency);
4036 static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency)
4038 struct mxl5005s_state *state = fe->tuner_priv;
4046 static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
4048 struct mxl5005s_state *state = fe->tuner_priv;
4056 static int mxl5005s_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
4058 struct mxl5005s_state *state = fe->tuner_priv;
4066 static int mxl5005s_release(struct dvb_frontend *fe)
4069 kfree(fe->tuner_priv);
4070 fe->tuner_priv = NULL;
4091 struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
4102 state->frontend = fe;
4109 memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops,
4112 fe->tuner_priv = state;
4113 return fe;