Lines Matching refs:status
67 int status;
70 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
73 return status;
119 int status;
122 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
125 return status;
130 int status = 0;
137 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
138 if (status < 0)
139 return status;
141 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
142 if (status < 0)
143 return status;
147 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
148 if (status < 0)
149 return status;
151 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
152 if (status < 0)
153 return status;
157 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
158 if (status < 0) {
164 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
166 if (status < 0) {
175 status = -1;
180 if (status < 0)
181 return status;
184 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
185 if (status < 0)
186 return status;
191 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
193 return status;
198 int status = 0;
201 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
202 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
203 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
206 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
209 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
210 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
214 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
215 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
216 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
220 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
221 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
222 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
225 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
226 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
227 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
230 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
232 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
234 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
238 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
239 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
240 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
242 return status;
248 int status = 0;
250 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
252 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
254 return status;
271 int status = 0;
275 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
279 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
283 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
287 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
293 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
297 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
300 return status;
305 int status = 0;
317 status = cx231xx_afe_setup_AFE_for_baseband(dev);
332 status = cx231xx_afe_adjust_ref_count(dev,
337 return status;
344 int status = 0;
364 status = afe_write_byte(dev, SUP_BLK_PWRDN,
367 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
369 if (status < 0)
373 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
375 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
377 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
380 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
382 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
384 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
387 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
392 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
397 status = afe_write_byte(dev, SUP_BLK_PWRDN,
400 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
402 if (status < 0)
406 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
408 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
410 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
414 status = -1;
421 status = afe_write_byte(dev, SUP_BLK_PWRDN,
424 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
426 if (status < 0)
430 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
432 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
434 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
437 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
439 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
441 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
444 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
449 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
454 status = afe_write_byte(dev, SUP_BLK_PWRDN,
457 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
459 if (status < 0)
463 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
465 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
467 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
471 status = -1;
475 return status;
482 int status = 0;
487 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
488 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
491 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
492 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
515 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
517 return status;
531 int status;
534 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
537 return status;
554 int status = 0;
555 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
556 if (status < 0)
557 return status;
565 int status = 0;
573 status = cx231xx_set_power_mode(dev,
575 if (status < 0) {
578 __func__, status);
579 return status;
582 status = cx231xx_set_decoder_video_input(dev,
591 status = cx231xx_set_power_mode(dev,
593 if (status < 0) {
596 __func__, status);
597 return status;
601 status = cx231xx_set_decoder_video_input(dev,
605 status = cx231xx_set_decoder_video_input(dev,
619 return status;
625 int status = 0;
629 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
630 if (status < 0) {
633 __func__, status);
634 return status;
639 status = cx231xx_afe_set_input_mux(dev, input);
640 if (status < 0) {
643 __func__, status);
644 return status;
649 status = vid_blk_read_word(dev, AFE_CTRL, &value);
657 status = vid_blk_write_word(dev, AFE_CTRL, value);
659 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
661 status = vid_blk_write_word(dev, OUT_CTRL1, value);
664 status = cx231xx_read_modify_write_i2c_dword(dev,
671 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
672 if (status < 0) {
675 __func__, status);
676 return status;
680 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
689 status = vid_blk_write_word(dev, DFE_CTRL1, value);
692 status = cx231xx_read_modify_write_i2c_dword(dev,
698 status = cx231xx_read_modify_write_i2c_dword(dev,
706 status = vid_blk_read_word(dev, AFE_CTRL, &value);
713 status = vid_blk_write_word(dev, AFE_CTRL, value);
716 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
717 if (status < 0) {
720 __func__, status);
721 return status;
725 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
734 status = vid_blk_write_word(dev, DFE_CTRL1, value);
737 status = cx231xx_read_modify_write_i2c_dword(dev,
743 status = cx231xx_read_modify_write_i2c_dword(dev,
750 status = vid_blk_read_word(dev, AFE_CTRL, &value);
758 status = vid_blk_write_word(dev, AFE_CTRL, value);
760 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
769 status = vid_blk_read_word(dev, AFE_CTRL, &value);
777 status = vid_blk_write_word(dev, AFE_CTRL, value);
779 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
781 status = vid_blk_write_word(dev, OUT_CTRL1, value);
784 status = cx231xx_read_modify_write_i2c_dword(dev,
790 status = cx231xx_dif_set_standard(dev,
792 if (status < 0) {
795 __func__, status);
796 return status;
800 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
809 status = vid_blk_write_word(dev, DFE_CTRL1, value);
812 status = cx231xx_read_modify_write_i2c_dword(dev,
818 status = cx231xx_read_modify_write_i2c_dword(dev,
827 status = cx231xx_dif_set_standard(dev, dev->norm);
828 if (status < 0) {
831 __func__, status);
832 return status;
836 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
842 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
845 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
855 status = vid_blk_write_word(dev, DFE_CTRL1, value);
864 status = vid_blk_write_word(dev, DFE_CTRL1, value);
867 status = vid_blk_read_word(dev, PIN_CTRL, &value);
871 status = vid_blk_write_word(dev, PIN_CTRL, value);
874 status = cx231xx_read_modify_write_i2c_dword(dev,
880 status = cx231xx_read_modify_write_i2c_dword(dev,
886 status = cx231xx_read_modify_write_i2c_dword(dev,
897 status = vid_blk_read_word(dev, AFE_CTRL, &value);
905 status = vid_blk_write_word(dev, AFE_CTRL, value);
908 status = vid_blk_read_word(dev, PIN_CTRL,
910 status = vid_blk_write_word(dev, PIN_CTRL,
921 status = cx231xx_read_modify_write_i2c_dword(dev,
926 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
929 status = vid_blk_write_word(dev, OUT_CTRL1, value);
932 return status;
971 int status = 0;
977 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
984 status = cx231xx_read_modify_write_i2c_dword(dev,
988 status = cx231xx_read_modify_write_i2c_dword(dev,
993 status = cx231xx_read_modify_write_i2c_dword(dev,
999 status = cx231xx_read_modify_write_i2c_dword(dev,
1008 status = cx231xx_read_modify_write_i2c_dword(dev,
1012 status = cx231xx_read_modify_write_i2c_dword(dev,
1019 status = cx231xx_read_modify_write_i2c_dword(dev,
1027 status = cx231xx_read_modify_write_i2c_dword(dev,
1035 status = cx231xx_read_modify_write_i2c_dword(dev,
1039 status = cx231xx_read_modify_write_i2c_dword(dev,
1046 status = cx231xx_read_modify_write_i2c_dword(dev,
1054 status = cx231xx_read_modify_write_i2c_dword(dev,
1063 return status;
1084 int status = 0;
1092 status = cx231xx_i2s_blk_set_audio_input(dev, input);
1099 status = cx231xx_set_audio_decoder_input(dev, ainput);
1101 return status;
1108 int status;
1113 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1115 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1122 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
1127 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
1129 status = vid_blk_write_word(dev, AC97_CTL,
1133 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1140 status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
1141 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
1144 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
1145 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
1149 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
1150 status = vid_blk_write_word(dev, PATH1_SC_CTL,
1156 status = stopAudioFirmware(dev);
1158 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1174 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1181 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1184 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1186 status = restartAudioFirmware(dev);
1191 status = cx231xx_read_modify_write_i2c_dword(dev,
1199 status = cx231xx_read_modify_write_i2c_dword(dev,
1222 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1227 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1229 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1231 return status;
1240 int status = 0;
1242 status = vid_blk_read_word(dev, PIN_CTRL, &value);
1244 status = vid_blk_write_word(dev, PIN_CTRL, value);
1246 return status;
1252 int status = 0;
1255 status = cx231xx_set_gpio_direction(dev,
1260 status = cx231xx_set_gpio_value(dev,
1264 return status;
1270 int status = 0;
1275 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1277 if (status < 0)
1278 return status;
1294 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1297 return status;
1305 u8 status = 0;
1312 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1314 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1614 int status = 0;
1620 status = cx231xx_reg_mask_write(dev,
1624 status = cx231xx_reg_mask_write(dev,
1628 status = cx231xx_reg_mask_write(dev,
1632 status = cx231xx_reg_mask_write(dev,
1638 status = cx231xx_reg_mask_write(dev,
1642 status = cx231xx_reg_mask_write(dev,
1647 status = cx231xx_reg_mask_write(dev,
1651 status = cx231xx_reg_mask_write(dev,
1655 status = cx231xx_reg_mask_write(dev,
1663 status = cx231xx_reg_mask_write(dev,
1667 status = cx231xx_reg_mask_write(dev,
1672 status = cx231xx_reg_mask_write(dev,
1676 status = cx231xx_reg_mask_write(dev,
1683 status = cx231xx_reg_mask_write(dev,
1687 status = cx231xx_reg_mask_write(dev,
1692 status = cx231xx_reg_mask_write(dev,
1696 status = cx231xx_reg_mask_write(dev,
1702 return status;
1707 int status = 0;
1713 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1737 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1743 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1744 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1747 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1750 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1752 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1754 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1756 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1758 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1760 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1762 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1764 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1766 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1769 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1772 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1775 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1778 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1780 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1783 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1786 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1789 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1795 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1797 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1799 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1801 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1803 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1805 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1807 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1809 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1811 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1814 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1817 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1820 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1823 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1825 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1828 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1831 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1834 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1841 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1842 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1843 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1844 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1845 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1846 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1848 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1850 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1852 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1854 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1855 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1857 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1859 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1861 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1868 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1869 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1870 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1871 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1872 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1873 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1875 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1877 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1879 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1881 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1883 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1885 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1887 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1889 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1898 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1900 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1902 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1904 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1906 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1908 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1910 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1912 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1914 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1917 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1920 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1923 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1925 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1928 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1931 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1934 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1936 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1945 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1947 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1949 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1951 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1953 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1955 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1957 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1959 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1961 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1964 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1967 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1970 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1972 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1975 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1978 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1981 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1983 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2001 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
2002 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
2003 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
2004 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
2005 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
2006 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
2008 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
2010 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
2012 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
2014 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
2016 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
2018 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
2020 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
2023 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
2024 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
2026 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
2033 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2035 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2037 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2039 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2041 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2043 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2045 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2047 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2049 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2052 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2055 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2058 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2061 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2063 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2066 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2069 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2072 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2090 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
2092 return status;
2097 int status = 0;
2101 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2105 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2107 return status;
2112 int status = 0;
2118 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2136 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2138 return status == sizeof(dwval) ? 0 : -EIO;
2146 int status = 0;
2149 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2153 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2156 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2159 return status;
2165 int status = 0;
2169 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2172 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2175 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2179 return status;
2185 int status = 0;
2189 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2191 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2201 return status;
2211 int status = 0;
2221 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2223 if (status < 0)
2224 return status;
2238 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2247 status =
2257 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2272 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2282 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2293 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2303 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2314 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2340 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2350 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2360 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2371 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2381 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2419 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2425 status = cx231xx_afe_update_power_control(dev, mode);
2428 status = cx231xx_i2s_blk_update_power_control(dev, mode);
2430 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2433 return status;
2440 int status = 0;
2442 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
2444 if (status > 0)
2445 return status;
2454 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2457 return status;
2467 int status = 0;
2470 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
2472 if (status < 0)
2473 return status;
2482 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2485 return status;
2492 int status = 0;
2495 status =
2497 if (status < 0)
2498 return status;
2507 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2510 return status;
2515 int status = 0;
2523 status =
2529 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2534 status =
2540 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2551 status = cx231xx_mode_register(dev, TS_MODE_REG, value);
2557 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2564 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2569 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2570 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010);
2577 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2578 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2582 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2585 return status;
2645 int status = 0;
2648 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&gpio_val, 4, 0, 0);
2650 return status;
2656 int status = 0;
2658 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&tmp, 4, 0, 1);
2661 return status;
2678 int status = 0;
2691 status = cx231xx_set_gpio_bit(dev, value, dev->gpio_val);
2696 return status;
2712 int status = 0;
2724 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2738 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2740 return status;
2748 int status = 0;
2756 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2757 if (status < 0)
2764 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2765 if (status < 0)
2772 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2773 if (status < 0)
2776 return status;
2781 int status = 0;
2790 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2791 if (status < 0)
2798 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2799 if (status < 0)
2807 status =
2809 if (status < 0)
2812 return status;
2817 int status = 0;
2829 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2834 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2839 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2845 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2850 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2855 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2859 return status;
2865 int status = 0;
2874 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2879 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2884 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2896 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2901 return status;
2906 int status = 0;
2917 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2921 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2937 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, &dev->gpio_val);
2942 status = 0;
2953 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2955 return status;
2960 int status = 0;
2964 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2969 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2973 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2977 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2981 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2983 return status;
2988 int status = 0;
2993 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2997 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
3001 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
3003 return status;
3014 int status = 0;
3021 status = cx231xx_gpio_i2c_start(dev);
3024 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
3027 status = cx231xx_gpio_i2c_read_ack(dev);
3033 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
3037 status = cx231xx_gpio_i2c_write_ack(dev);
3042 status = cx231xx_gpio_i2c_write_nak(dev);
3045 status = cx231xx_gpio_i2c_end(dev);
3050 return status;