Lines Matching refs:ret

57 	int ret;
60 ret = mxl111sf_write_reg(state, 0xff, 0x00); /* AIC */
61 if (mxl_fail(ret))
63 ret = mxl111sf_write_reg(state, 0x02, 0x01); /* get out of reset */
64 mxl_fail(ret);
66 return ret;
71 int ret;
77 ret = mxl111sf_write_reg(state, 0x03,
79 if (mxl_fail(ret))
82 ret = mxl111sf_write_reg_mask(state,
88 if (mxl_fail(ret))
93 return ret;
126 int ret;
133 ret = mxl111sf_write_reg(state, V6_PIN_MUX_MODE_REG, V6_ENABLE_PIN_MUX);
134 mxl_fail(ret);
144 ret = mxl111sf_write_reg(state, V6_MPEG_IN_CLK_INV_REG, mode);
145 mxl_fail(ret);
149 ret = mxl111sf_read_reg(state, V6_MPEG_IN_CTRL_REG, &mode);
150 mxl_fail(ret);
168 ret = mxl111sf_read_reg(state,
171 mxl_fail(ret);
178 ret = mxl111sf_write_reg(state,
181 mxl_fail(ret);
196 ret = mxl111sf_write_reg(state, V6_MPEG_IN_CTRL_REG, mode);
197 mxl_fail(ret);
199 return ret;
218 int ret;
222 ret = mxl111sf_ctrl_program_regs(state, init_i2s);
223 if (mxl_fail(ret))
226 ret = mxl111sf_write_reg(state, V6_I2S_NUM_SAMPLES_REG, sample_size);
227 mxl_fail(ret);
229 return ret;
247 int ret;
252 ret = mxl111sf_read_reg(state, V6_I2S_STREAM_START_BIT_REG, &tmp);
253 if (mxl_fail(ret))
258 ret = mxl111sf_write_reg(state, V6_I2S_STREAM_START_BIT_REG, tmp);
259 if (mxl_fail(ret))
262 ret = mxl111sf_read_reg(state, V6_I2S_STREAM_END_BIT_REG, &tmp);
263 if (mxl_fail(ret))
268 ret = mxl111sf_write_reg(state, V6_I2S_STREAM_END_BIT_REG, tmp);
269 mxl_fail(ret);
271 return ret;
277 int ret;
281 ret = mxl111sf_write_reg(state, 0x00, 0x02);
282 if (mxl_fail(ret))
285 ret = mxl111sf_read_reg(state, V8_SPI_MODE_REG, &val);
286 if (mxl_fail(ret))
294 ret = mxl111sf_write_reg(state, V8_SPI_MODE_REG, val);
295 if (mxl_fail(ret))
298 ret = mxl111sf_write_reg(state, 0x00, 0x00);
299 mxl_fail(ret);
301 return ret;
308 int ret;
328 ret = mxl111sf_write_reg(state, V6_IDAC_HYSTERESIS_REG,
330 mxl_fail(ret);
333 ret = mxl111sf_write_reg(state, V6_IDAC_SETTINGS_REG, val);
334 mxl_fail(ret);
336 return ret;