Lines Matching refs:host
30 #include <linux/mmc/host.h>
85 static bool dw_mci_reset(struct dw_mci *host);
97 spin_lock_bh(&slot->host->lock);
123 spin_unlock_bh(&slot->host->lock);
169 struct dw_mci *host = slot->host;
177 node = debugfs_create_file("regs", S_IRUSR, root, host,
187 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
192 (u32 *)&host->pending_events);
197 (u32 *)&host->completed_events);
214 struct dw_mci *host = slot->host;
215 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
237 WARN_ON(slot->host->state != STATE_SENDING_CMD);
238 slot->host->state = STATE_SENDING_CMD11;
251 clk_en_a = mci_readl(host, CLKENA);
253 mci_writel(host, CLKENA, clk_en_a);
278 drv_data->prepare_command(slot->host, &cmdr);
283 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
291 stop = &host->stop_abort;
317 static void dw_mci_start_command(struct dw_mci *host,
320 host->cmd = cmd;
321 dev_vdbg(host->dev,
325 mci_writel(host, CMDARG, cmd->arg);
328 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
331 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
333 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
334 dw_mci_start_command(host, stop, host->stop_cmdr);
338 static void dw_mci_stop_dma(struct dw_mci *host)
340 if (host->using_dma) {
341 host->dma_ops->stop(host);
342 host->dma_ops->cleanup(host);
346 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
358 static void dw_mci_dma_cleanup(struct dw_mci *host)
360 struct mmc_data *data = host->data;
364 dma_unmap_sg(host->dev,
370 static void dw_mci_idmac_reset(struct dw_mci *host)
372 u32 bmod = mci_readl(host, BMOD);
375 mci_writel(host, BMOD, bmod);
378 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
383 temp = mci_readl(host, CTRL);
386 mci_writel(host, CTRL, temp);
389 temp = mci_readl(host, BMOD);
392 mci_writel(host, BMOD, temp);
395 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
397 struct mmc_data *data = host->data;
399 dev_vdbg(host->dev, "DMA complete\n");
401 host->dma_ops->cleanup(host);
408 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
409 tasklet_schedule(&host->tasklet);
413 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
417 struct idmac_desc *desc = host->sg_cpu;
434 desc = host->sg_cpu;
438 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
445 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
449 dw_mci_translate_sglist(host, host->data, sg_len);
452 temp = mci_readl(host, CTRL);
454 mci_writel(host, CTRL, temp);
459 temp = mci_readl(host, BMOD);
461 mci_writel(host, BMOD, temp);
464 mci_writel(host, PLDMND, 1);
467 static int dw_mci_idmac_init(struct dw_mci *host)
473 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
476 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
477 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
480 p->des3 = host->sg_dma;
483 dw_mci_idmac_reset(host);
486 mci_writel(host, IDSTS, IDMAC_INT_CLR);
487 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
491 mci_writel(host, DBADDR, host->sg_dma);
504 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
530 sg_len = dma_map_sg(host->dev,
550 if (!slot->host->use_dma || !data)
558 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
569 if (!slot->host->use_dma || !data)
573 dma_unmap_sg(slot->host->dev,
580 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
585 u32 fifo_width = 1 << host->data_shift;
590 tx_wmark = (host->fifo_depth) / 2;
591 tx_wmark_invers = host->fifo_depth - tx_wmark;
617 mci_writel(host, FIFOTH, fifoth_val);
621 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
629 if (host->timing != MMC_TIMING_MMC_HS200 &&
630 host->timing != MMC_TIMING_UHS_SDR104)
633 blksz_depth = blksz / (1 << host->data_shift);
634 fifo_depth = host->fifo_depth;
645 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
649 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
652 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
657 host->using_dma = 0;
660 if (!host->use_dma)
663 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
665 host->dma_ops->stop(host);
669 host->using_dma = 1;
671 dev_vdbg(host->dev,
673 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
681 if (host->prev_blksz != data->blksz)
682 dw_mci_adjust_fifoth(host, data);
685 temp = mci_readl(host, CTRL);
687 mci_writel(host, CTRL, temp);
690 temp = mci_readl(host, INTMASK);
692 mci_writel(host, INTMASK, temp);
694 host->dma_ops->start(host, sg_len);
699 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
705 WARN_ON(host->data);
706 host->sg = NULL;
707 host->data = data;
710 host->dir_status = DW_MCI_RECV_STATUS;
711 dw_mci_ctrl_rd_thld(host, data);
713 host->dir_status = DW_MCI_SEND_STATUS;
716 if (dw_mci_submit_data_dma(host, data)) {
718 if (host->data->flags & MMC_DATA_READ)
723 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
724 host->sg = data->sg;
725 host->part_buf_start = 0;
726 host->part_buf_count = 0;
728 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
729 temp = mci_readl(host, INTMASK);
731 mci_writel(host, INTMASK, temp);
733 temp = mci_readl(host, CTRL);
735 mci_writel(host, CTRL, temp);
742 mci_writel(host, FIFOTH, host->fifoth_val);
743 host->prev_blksz = 0;
750 host->prev_blksz = data->blksz;
756 struct dw_mci *host = slot->host;
760 mci_writel(host, CMDARG, arg);
762 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
765 cmd_status = mci_readl(host, CMD);
776 struct dw_mci *host = slot->host;
783 if (host->state == STATE_WAITING_CMD11_DONE)
787 mci_writel(host, CLKENA, 0);
789 } else if (clock != host->current_speed || force_clkinit) {
790 div = host->bus_hz / clock;
791 if (host->bus_hz % clock && host->bus_hz > clock)
798 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
803 slot->id, host->bus_hz, clock,
804 div ? ((host->bus_hz / div) >> 1) :
805 host->bus_hz, div);
808 mci_writel(host, CLKENA, 0);
809 mci_writel(host, CLKSRC, 0);
815 mci_writel(host, CLKDIV, div);
822 if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id)))
824 mci_writel(host, CLKENA, clk_en_a);
833 host->current_speed = clock;
836 mci_writel(host, CTYPE, (slot->ctype << slot->id));
839 static void __dw_mci_start_request(struct dw_mci *host,
849 host->cur_slot = slot;
850 host->mrq = mrq;
852 host->pending_events = 0;
853 host->completed_events = 0;
854 host->cmd_status = 0;
855 host->data_status = 0;
856 host->dir_status = 0;
860 mci_writel(host, TMOUT, 0xFFFFFFFF);
861 mci_writel(host, BYTCNT, data->blksz*data->blocks);
862 mci_writel(host, BLKSIZ, data->blksz);
872 dw_mci_submit_data(host, data);
876 dw_mci_start_command(host, cmd, cmdflags);
879 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
881 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
884 static void dw_mci_start_request(struct dw_mci *host,
891 __dw_mci_start_request(host, slot, cmd);
894 /* must be called with host->lock held */
895 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
899 host->state);
903 if (host->state == STATE_WAITING_CMD11_DONE) {
911 host->state = STATE_IDLE;
914 if (host->state == STATE_IDLE) {
915 host->state = STATE_SENDING_CMD;
916 dw_mci_start_request(host, slot);
918 list_add_tail(&slot->queue_node, &host->queue);
925 struct dw_mci *host = slot->host;
934 spin_lock_bh(&host->lock);
937 spin_unlock_bh(&host->lock);
943 dw_mci_queue_request(host, slot, mrq);
945 spin_unlock_bh(&host->lock);
951 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
967 regs = mci_readl(slot->host, UHS_REG);
975 mci_writel(slot->host, UHS_REG, regs);
976 slot->host->timing = ios->timing;
985 drv_data->set_ios(slot->host, ios);
990 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
991 slot->host->state = STATE_IDLE;
999 dev_err(slot->host->dev,
1005 if (!IS_ERR(mmc->supply.vqmmc) && !slot->host->vqmmc_enabled) {
1008 dev_err(slot->host->dev,
1011 slot->host->vqmmc_enabled = true;
1014 regs = mci_readl(slot->host, PWREN);
1016 mci_writel(slot->host, PWREN, regs);
1022 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) {
1024 slot->host->vqmmc_enabled = false;
1027 regs = mci_readl(slot->host, PWREN);
1029 mci_writel(slot->host, PWREN, regs);
1045 status = mci_readl(slot->host, STATUS);
1053 struct dw_mci *host = slot->host;
1064 uhs = mci_readl(host, UHS_REG);
1084 mci_writel(host, UHS_REG, uhs);
1097 (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT))
1103 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1115 struct dw_mci_board *brd = slot->host->pdata;
1116 struct dw_mci *host = slot->host;
1125 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1128 spin_lock_bh(&host->lock);
1136 spin_unlock_bh(&host->lock);
1152 struct dw_mci *host = slot->host;
1156 clk_en_a = mci_readl(host, CLKENA);
1159 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
1168 struct dw_mci *host = slot->host;
1172 int_mask = mci_readl(host, INTMASK);
1182 mci_writel(host, INTMASK,
1185 mci_writel(host, INTMASK,
1193 struct dw_mci *host = slot->host;
1194 const struct dw_mci_drv_data *drv_data = host->drv_data;
1212 dev_err(host->dev,
1236 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1237 __releases(&host->lock)
1238 __acquires(&host->lock)
1241 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1243 WARN_ON(host->cmd || host->data);
1245 host->cur_slot->mrq = NULL;
1246 host->mrq = NULL;
1247 if (!list_empty(&host->queue)) {
1248 slot = list_entry(host->queue.next,
1251 dev_vdbg(host->dev, "list not empty: %s is next\n",
1253 host->state = STATE_SENDING_CMD;
1254 dw_mci_start_request(host, slot);
1256 dev_vdbg(host->dev, "list empty\n");
1258 if (host->state == STATE_SENDING_CMD11)
1259 host->state = STATE_WAITING_CMD11_DONE;
1261 host->state = STATE_IDLE;
1264 spin_unlock(&host->lock);
1266 spin_lock(&host->lock);
1269 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1271 u32 status = host->cmd_status;
1273 host->cmd_status = 0;
1278 cmd->resp[3] = mci_readl(host, RESP0);
1279 cmd->resp[2] = mci_readl(host, RESP1);
1280 cmd->resp[1] = mci_readl(host, RESP2);
1281 cmd->resp[0] = mci_readl(host, RESP3);
1283 cmd->resp[0] = mci_readl(host, RESP0);
1301 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1308 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1310 u32 status = host->data_status;
1318 if (host->dir_status ==
1327 } else if (host->dir_status ==
1336 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1342 dw_mci_reset(host);
1353 struct dw_mci *host = (struct dw_mci *)priv;
1361 spin_lock(&host->lock);
1363 state = host->state;
1364 data = host->data;
1365 mrq = host->mrq;
1378 &host->pending_events))
1381 cmd = host->cmd;
1382 host->cmd = NULL;
1383 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1384 err = dw_mci_command_complete(host, cmd);
1387 __dw_mci_start_request(host, host->cur_slot,
1393 dw_mci_stop_dma(host);
1394 send_stop_abort(host, data);
1400 dw_mci_request_end(host, mrq);
1417 &host->pending_events)) {
1418 dw_mci_stop_dma(host);
1419 send_stop_abort(host, data);
1425 &host->pending_events))
1428 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1444 &host->pending_events)) {
1445 dw_mci_stop_dma(host);
1446 send_stop_abort(host, data);
1456 &host->pending_events))
1459 host->data = NULL;
1460 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1461 err = dw_mci_data_complete(host, data);
1467 dw_mci_request_end(host, mrq);
1473 send_stop_abort(host, data);
1485 &host->pending_events)) {
1486 host->cmd = NULL;
1487 dw_mci_request_end(host, mrq);
1502 &host->pending_events))
1507 dw_mci_reset(host);
1509 host->cmd = NULL;
1510 host->data = NULL;
1513 dw_mci_command_complete(host, mrq->stop);
1515 host->cmd_status = 0;
1517 dw_mci_request_end(host, mrq);
1522 &host->pending_events))
1530 host->state = state;
1532 spin_unlock(&host->lock);
1537 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1539 memcpy((void *)&host->part_buf, buf, cnt);
1540 host->part_buf_count = cnt;
1544 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1546 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1547 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1548 host->part_buf_count += cnt;
1553 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1555 cnt = min(cnt, (int)host->part_buf_count);
1557 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1559 host->part_buf_count -= cnt;
1560 host->part_buf_start += cnt;
1566 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1568 memcpy(buf, &host->part_buf, cnt);
1569 host->part_buf_start = cnt;
1570 host->part_buf_count = (1 << host->data_shift) - cnt;
1573 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1575 struct mmc_data *data = host->data;
1579 if (unlikely(host->part_buf_count)) {
1580 int len = dw_mci_push_part_bytes(host, buf, cnt);
1583 if (host->part_buf_count == 2) {
1584 mci_writew(host, DATA(host->data_offset),
1585 host->part_buf16);
1586 host->part_buf_count = 0;
1602 mci_writew(host, DATA(host->data_offset),
1610 mci_writew(host, DATA(host->data_offset), *pdata++);
1615 dw_mci_set_part_bytes(host, buf, cnt);
1619 mci_writew(host, DATA(host->data_offset),
1620 host->part_buf16);
1624 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1635 aligned_buf[i] = mci_readw(host,
1636 DATA(host->data_offset));
1647 *pdata++ = mci_readw(host, DATA(host->data_offset));
1651 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
1652 dw_mci_pull_final_bytes(host, buf, cnt);
1656 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1658 struct mmc_data *data = host->data;
1662 if (unlikely(host->part_buf_count)) {
1663 int len = dw_mci_push_part_bytes(host, buf, cnt);
1666 if (host->part_buf_count == 4) {
1667 mci_writel(host, DATA(host->data_offset),
1668 host->part_buf32);
1669 host->part_buf_count = 0;
1685 mci_writel(host, DATA(host->data_offset),
1693 mci_writel(host, DATA(host->data_offset), *pdata++);
1698 dw_mci_set_part_bytes(host, buf, cnt);
1702 mci_writel(host, DATA(host->data_offset),
1703 host->part_buf32);
1707 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1718 aligned_buf[i] = mci_readl(host,
1719 DATA(host->data_offset));
1730 *pdata++ = mci_readl(host, DATA(host->data_offset));
1734 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
1735 dw_mci_pull_final_bytes(host, buf, cnt);
1739 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1741 struct mmc_data *data = host->data;
1745 if (unlikely(host->part_buf_count)) {
1746 int len = dw_mci_push_part_bytes(host, buf, cnt);
1750 if (host->part_buf_count == 8) {
1751 mci_writeq(host, DATA(host->data_offset),
1752 host->part_buf);
1753 host->part_buf_count = 0;
1769 mci_writeq(host, DATA(host->data_offset),
1777 mci_writeq(host, DATA(host->data_offset), *pdata++);
1782 dw_mci_set_part_bytes(host, buf, cnt);
1786 mci_writeq(host, DATA(host->data_offset),
1787 host->part_buf);
1791 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1802 aligned_buf[i] = mci_readq(host,
1803 DATA(host->data_offset));
1814 *pdata++ = mci_readq(host, DATA(host->data_offset));
1818 host->part_buf = mci_readq(host, DATA(host->data_offset));
1819 dw_mci_pull_final_bytes(host, buf, cnt);
1823 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1828 len = dw_mci_pull_part_bytes(host, buf, cnt);
1835 host->pull_data(host, buf, cnt);
1838 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
1840 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1843 struct mmc_data *data = host->data;
1844 int shift = host->data_shift;
1853 host->sg = sg_miter->piter.sg;
1859 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1860 << shift) + host->part_buf_count;
1864 dw_mci_pull_data(host, (void *)(buf + offset), len);
1871 status = mci_readl(host, MINTSTS);
1872 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1875 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
1887 host->sg = NULL;
1889 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1892 static void dw_mci_write_data_pio(struct dw_mci *host)
1894 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1897 struct mmc_data *data = host->data;
1898 int shift = host->data_shift;
1901 unsigned int fifo_depth = host->fifo_depth;
1908 host->sg = sg_miter->piter.sg;
1915 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
1916 << shift) - host->part_buf_count;
1920 host->push_data(host, (void *)(buf + offset), len);
1927 status = mci_readl(host, MINTSTS);
1928 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1941 host->sg = NULL;
1943 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1946 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1948 if (!host->cmd_status)
1949 host->cmd_status = status;
1953 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1954 tasklet_schedule(&host->tasklet);
1959 struct dw_mci *host = dev_id;
1963 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1969 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1971 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1977 if ((host->state == STATE_SENDING_CMD11) &&
1979 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
1981 dw_mci_cmd_interrupt(host, pending);
1985 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1986 host->cmd_status = pending;
1988 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1993 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1994 host->data_status = pending;
1996 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1997 tasklet_schedule(&host->tasklet);
2001 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2002 if (!host->data_status)
2003 host->data_status = pending;
2005 if (host->dir_status == DW_MCI_RECV_STATUS) {
2006 if (host->sg != NULL)
2007 dw_mci_read_data_pio(host, true);
2009 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2010 tasklet_schedule(&host->tasklet);
2014 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2015 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2016 dw_mci_read_data_pio(host, false);
2020 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2021 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2022 dw_mci_write_data_pio(host);
2026 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2027 dw_mci_cmd_interrupt(host, pending);
2031 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2032 queue_work(host->card_workqueue, &host->card_work);
2036 for (i = 0; i < host->num_slots; i++) {
2037 struct dw_mci_slot *slot = host->slot[i];
2039 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
2048 pending = mci_readl(host, IDSTS);
2050 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
2051 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2052 host->dma_ops->complete(host);
2061 struct dw_mci *host = container_of(work, struct dw_mci, card_work);
2064 for (i = 0; i < host->num_slots; i++) {
2065 struct dw_mci_slot *slot = host->slot[i];
2075 spin_lock_bh(&host->lock);
2083 if (mrq == host->mrq) {
2084 host->data = NULL;
2085 host->cmd = NULL;
2087 switch (host->state) {
2099 dw_mci_stop_dma(host);
2112 dw_mci_request_end(host, mrq);
2121 spin_unlock(&host->lock);
2123 spin_lock(&host->lock);
2129 dw_mci_reset(host);
2131 spin_unlock_bh(&host->lock);
2137 msecs_to_jiffies(host->pdata->detect_delay_ms));
2195 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2199 const struct dw_mci_drv_data *drv_data = host->drv_data;
2203 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2210 slot->host = host;
2211 host->slot[id] = slot;
2213 slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
2216 if (of_property_read_u32_array(host->dev->of_node,
2233 if (host->pdata->caps)
2234 mmc->caps = host->pdata->caps;
2236 if (host->pdata->pm_caps)
2237 mmc->pm_caps = host->pdata->pm_caps;
2239 if (host->dev->of_node) {
2240 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2244 ctrl_id = to_platform_device(host->dev)->id;
2249 if (host->pdata->caps2)
2250 mmc->caps2 = host->pdata->caps2;
2256 if (host->pdata->blk_settings) {
2257 mmc->max_segs = host->pdata->blk_settings->max_segs;
2258 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
2259 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
2260 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
2261 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
2265 mmc->max_segs = host->ring_size;
2267 mmc->max_blk_count = host->ring_size;
2306 slot->host->slot[id] = NULL;
2310 static void dw_mci_init_dma(struct dw_mci *host)
2313 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2314 &host->sg_dma, GFP_KERNEL);
2315 if (!host->sg_cpu) {
2316 dev_err(host->dev, "%s: could not alloc DMA memory\n",
2323 host->dma_ops = &dw_mci_idmac_ops;
2324 dev_info(host->dev, "Using internal DMA controller.\n");
2327 if (!host->dma_ops)
2330 if (host->dma_ops->init && host->dma_ops->start &&
2331 host->dma_ops->stop && host->dma_ops->cleanup) {
2332 if (host->dma_ops->init(host)) {
2333 dev_err(host->dev, "%s: Unable to initialize "
2338 dev_err(host->dev, "DMA initialization not found.\n");
2342 host->use_dma = 1;
2346 dev_info(host->dev, "Using PIO mode.\n");
2347 host->use_dma = 0;
2351 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2356 ctrl = mci_readl(host, CTRL);
2358 mci_writel(host, CTRL, ctrl);
2362 ctrl = mci_readl(host, CTRL);
2367 dev_err(host->dev,
2374 static bool dw_mci_reset(struct dw_mci *host)
2383 if (host->sg) {
2384 sg_miter_stop(&host->sg_miter);
2385 host->sg = NULL;
2388 if (host->use_dma)
2391 if (dw_mci_ctrl_reset(host, flags)) {
2396 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2399 if (host->use_dma) {
2403 status = mci_readl(host, STATUS);
2410 dev_err(host->dev,
2417 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2422 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2423 dev_err(host->dev, "%s: fifo/dma reset bits didn't "
2432 dw_mci_idmac_reset(host);
2439 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2458 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2461 struct device *dev = host->dev;
2463 const struct dw_mci_drv_data *drv_data = host->drv_data;
2496 ret = drv_data->parse_dt(host);
2508 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2514 int dw_mci_probe(struct dw_mci *host)
2516 const struct dw_mci_drv_data *drv_data = host->drv_data;
2521 if (!host->pdata) {
2522 host->pdata = dw_mci_parse_dt(host);
2523 if (IS_ERR(host->pdata)) {
2524 dev_err(host->dev, "platform data not available\n");
2529 if (host->pdata->num_slots > 1) {
2530 dev_err(host->dev,
2535 host->biu_clk = devm_clk_get(host->dev, "biu");
2536 if (IS_ERR(host->biu_clk)) {
2537 dev_dbg(host->dev, "biu clock not available\n");
2539 ret = clk_prepare_enable(host->biu_clk);
2541 dev_err(host->dev, "failed to enable biu clock\n");
2546 host->ciu_clk = devm_clk_get(host->dev, "ciu");
2547 if (IS_ERR(host->ciu_clk)) {
2548 dev_dbg(host->dev, "ciu clock not available\n");
2549 host->bus_hz = host->pdata->bus_hz;
2551 ret = clk_prepare_enable(host->ciu_clk);
2553 dev_err(host->dev, "failed to enable ciu clock\n");
2557 if (host->pdata->bus_hz) {
2558 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
2560 dev_warn(host->dev,
2562 host->pdata->bus_hz);
2564 host->bus_hz = clk_get_rate(host->ciu_clk);
2567 if (!host->bus_hz) {
2568 dev_err(host->dev,
2575 ret = drv_data->init(host);
2577 dev_err(host->dev,
2584 ret = drv_data->setup_clock(host);
2586 dev_err(host->dev,
2592 host->quirks = host->pdata->quirks;
2594 spin_lock_init(&host->lock);
2595 INIT_LIST_HEAD(&host->queue);
2598 * Get the host data width - this assumes that HCON has been set with
2601 i = (mci_readl(host, HCON) >> 7) & 0x7;
2603 host->push_data = dw_mci_push_data16;
2604 host->pull_data = dw_mci_pull_data16;
2606 host->data_shift = 1;
2608 host->push_data = dw_mci_push_data64;
2609 host->pull_data = dw_mci_pull_data64;
2611 host->data_shift = 3;
2615 "HCON reports a reserved host data width!\n"
2617 host->push_data = dw_mci_push_data32;
2618 host->pull_data = dw_mci_pull_data32;
2620 host->data_shift = 2;
2624 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
2627 host->dma_ops = host->pdata->dma_ops;
2628 dw_mci_init_dma(host);
2630 /* Clear the interrupts for the host controller */
2631 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2632 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2635 mci_writel(host, TMOUT, 0xFFFFFFFF);
2641 if (!host->pdata->fifo_depth) {
2648 fifo_size = mci_readl(host, FIFOTH);
2651 fifo_size = host->pdata->fifo_depth;
2653 host->fifo_depth = fifo_size;
2654 host->fifoth_val =
2656 mci_writel(host, FIFOTH, host->fifoth_val);
2659 mci_writel(host, CLKENA, 0);
2660 mci_writel(host, CLKSRC, 0);
2666 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
2667 dev_info(host->dev, "Version ID is %04x\n", host->verid);
2669 if (host->verid < DW_MMC_240A)
2670 host->data_offset = DATA_OFFSET;
2672 host->data_offset = DATA_240A_OFFSET;
2674 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
2675 host->card_workqueue = alloc_workqueue("dw-mci-card",
2677 if (!host->card_workqueue) {
2681 INIT_WORK(&host->card_work, dw_mci_work_routine_card);
2682 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
2683 host->irq_flags, "dw-mci", host);
2687 if (host->pdata->num_slots)
2688 host->num_slots = host->pdata->num_slots;
2690 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2696 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2697 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2700 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2702 dev_info(host->dev, "DW MMC controller at irq %d, "
2703 "%d bit host data width, "
2705 host->irq, width, fifo_size);
2708 for (i = 0; i < host->num_slots; i++) {
2709 ret = dw_mci_init_slot(host, i);
2711 dev_dbg(host->dev, "slot %d init failed\n", i);
2717 dev_info(host->dev, "%d slots initialized\n", init_slots);
2719 dev_dbg(host->dev, "attempted to initialize %d slots, "
2720 "but failed on all\n", host->num_slots);
2724 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2725 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
2730 destroy_workqueue(host->card_workqueue);
2733 if (host->use_dma && host->dma_ops->exit)
2734 host->dma_ops->exit(host);
2737 if (!IS_ERR(host->ciu_clk))
2738 clk_disable_unprepare(host->ciu_clk);
2741 if (!IS_ERR(host->biu_clk))
2742 clk_disable_unprepare(host->biu_clk);
2748 void dw_mci_remove(struct dw_mci *host)
2752 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2753 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2755 for (i = 0; i < host->num_slots; i++) {
2756 dev_dbg(host->dev, "remove slot %d\n", i);
2757 if (host->slot[i])
2758 dw_mci_cleanup_slot(host->slot[i], i);
2762 mci_writel(host, CLKENA, 0);
2763 mci_writel(host, CLKSRC, 0);
2765 destroy_workqueue(host->card_workqueue);
2767 if (host->use_dma && host->dma_ops->exit)
2768 host->dma_ops->exit(host);
2770 if (!IS_ERR(host->ciu_clk))
2771 clk_disable_unprepare(host->ciu_clk);
2773 if (!IS_ERR(host->biu_clk))
2774 clk_disable_unprepare(host->biu_clk);
2784 int dw_mci_suspend(struct dw_mci *host)
2790 int dw_mci_resume(struct dw_mci *host)
2794 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
2799 if (host->use_dma && host->dma_ops->init)
2800 host->dma_ops->init(host);
2806 mci_writel(host, FIFOTH, host->fifoth_val);
2807 host->prev_blksz = 0;
2810 mci_writel(host, TMOUT, 0xFFFFFFFF);
2812 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2813 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2816 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2818 for (i = 0; i < host->num_slots; i++) {
2819 struct dw_mci_slot *slot = host->slot[i];