Lines Matching refs:host
16 #include <linux/mmc/host.h>
165 static void jz4740_mmc_release_dma_channels(struct jz4740_mmc_host *host)
167 if (!host->use_dma)
170 dma_release_channel(host->dma_tx);
171 dma_release_channel(host->dma_rx);
174 static int jz4740_mmc_acquire_dma_channels(struct jz4740_mmc_host *host)
181 host->dma_tx = dma_request_channel(mask, NULL, host);
182 if (!host->dma_tx) {
183 dev_err(mmc_dev(host->mmc), "Failed to get dma_tx channel\n");
187 host->dma_rx = dma_request_channel(mask, NULL, host);
188 if (!host->dma_rx) {
189 dev_err(mmc_dev(host->mmc), "Failed to get dma_rx channel\n");
194 host->next_data.cookie = 1;
199 dma_release_channel(host->dma_tx);
208 static inline struct dma_chan *jz4740_mmc_get_dma_chan(struct jz4740_mmc_host *host,
211 return (data->flags & MMC_DATA_READ) ? host->dma_rx : host->dma_tx;
214 static void jz4740_mmc_dma_unmap(struct jz4740_mmc_host *host,
217 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
224 static int jz4740_mmc_prepare_dma_data(struct jz4740_mmc_host *host,
229 struct jz4740_mmc_host_next *next_data = &host->next_data;
234 data->host_cookie != host->next_data.cookie) {
235 dev_warn(mmc_dev(host->mmc),
236 "[%s] invalid cookie: data->host_cookie %d host->next_data.cookie %d\n",
239 host->next_data.cookie);
244 if (next || data->host_cookie != host->next_data.cookie) {
256 dev_err(mmc_dev(host->mmc),
265 host->sg_len = sg_len;
270 static int jz4740_mmc_start_dma_transfer(struct jz4740_mmc_host *host,
285 conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO;
287 chan = host->dma_tx;
290 conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO;
292 chan = host->dma_rx;
295 ret = jz4740_mmc_prepare_dma_data(host, data, NULL, chan);
302 host->sg_len,
306 dev_err(mmc_dev(host->mmc),
318 jz4740_mmc_dma_unmap(host, data);
326 struct jz4740_mmc_host *host = mmc_priv(mmc);
328 struct jz4740_mmc_host_next *next_data = &host->next_data;
332 if (host->use_dma) {
333 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
335 if (jz4740_mmc_prepare_dma_data(host, data, next_data, chan))
344 struct jz4740_mmc_host *host = mmc_priv(mmc);
347 if (host->use_dma && data->host_cookie) {
348 jz4740_mmc_dma_unmap(host, data);
353 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
361 static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
366 spin_lock_irqsave(&host->lock, flags);
368 host->irq_mask &= ~irq;
370 host->irq_mask |= irq;
371 spin_unlock_irqrestore(&host->lock, flags);
373 writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
376 static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
384 writew(val, host->base + JZ_REG_MMC_STRPCL);
387 static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
392 writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
394 status = readl(host->base + JZ_REG_MMC_STATUS);
398 static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
403 writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
406 status = readl(host->base + JZ_REG_MMC_STATUS);
410 static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
414 req = host->req;
415 host->req = NULL;
417 mmc_request_done(host->mmc, req);
420 static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host,
427 status = readw(host->base + JZ_REG_MMC_IREG);
431 set_bit(0, &host->waiting);
432 mod_timer(&host->timeout_timer, jiffies + 5*HZ);
433 jz4740_mmc_set_irq_enabled(host, irq, true);
440 static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host,
445 status = readl(host->base + JZ_REG_MMC_STATUS);
448 host->req->cmd->error = -ETIMEDOUT;
451 host->req->cmd->error = -EIO;
456 host->req->cmd->error = -ETIMEDOUT;
459 host->req->cmd->error = -EIO;
465 static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host,
468 struct sg_mapping_iter *miter = &host->miter;
469 void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO;
480 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
496 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
520 static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host,
523 struct sg_mapping_iter *miter = &host->miter;
524 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO;
537 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
555 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
579 status = readl(host->base + JZ_REG_MMC_STATUS);
582 status = readl(host->base + JZ_REG_MMC_STATUS);
597 struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data;
599 if (!test_and_clear_bit(0, &host->waiting))
602 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false);
604 host->req->cmd->error = -ETIMEDOUT;
605 jz4740_mmc_request_done(host);
608 static void jz4740_mmc_read_response(struct jz4740_mmc_host *host,
613 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO;
631 static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
634 uint32_t cmdat = host->cmdat;
636 host->cmdat &= ~JZ_MMC_CMDAT_INIT;
637 jz4740_mmc_clock_disable(host);
639 host->cmd = cmd;
665 if (host->use_dma)
668 writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
669 writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
672 writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
673 writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
674 writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
676 jz4740_mmc_clock_enable(host, 1);
679 static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host)
681 struct mmc_command *cmd = host->req->cmd;
690 sg_miter_start(&host->miter, data->sg, data->sg_len, direction);
696 struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
697 struct mmc_command *cmd = host->req->cmd;
698 struct mmc_request *req = host->req;
703 host->state = JZ4740_MMC_STATE_DONE;
705 switch (host->state) {
708 jz4740_mmc_read_response(host, cmd);
713 jz_mmc_prepare_data_transfer(host);
716 if (host->use_dma) {
723 timeout = jz4740_mmc_start_dma_transfer(host, data);
731 timeout = jz4740_mmc_read_data(host, data);
733 timeout = jz4740_mmc_write_data(host, data);
736 host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
740 jz4740_mmc_transfer_check_state(host, data);
742 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
744 host->state = JZ4740_MMC_STATE_SEND_STOP;
747 writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
753 jz4740_mmc_send_command(host, req->stop);
756 timeout = jz4740_mmc_poll_irq(host,
759 host->state = JZ4740_MMC_STATE_DONE;
768 jz4740_mmc_request_done(host);
775 struct jz4740_mmc_host *host = devid;
776 struct mmc_command *cmd = host->cmd;
779 irq_reg = readw(host->base + JZ_REG_MMC_IREG);
782 irq_reg &= ~host->irq_mask;
788 writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG);
791 writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
792 mmc_signal_sdio_irq(host->mmc);
796 if (host->req && cmd && irq_reg) {
797 if (test_and_clear_bit(0, &host->waiting)) {
798 del_timer(&host->timeout_timer);
800 status = readl(host->base + JZ_REG_MMC_STATUS);
813 jz4740_mmc_set_irq_enabled(host, irq_reg, false);
814 writew(irq_reg, host->base + JZ_REG_MMC_IREG);
823 static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
828 jz4740_mmc_clock_disable(host);
829 clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
831 real_rate = clk_get_rate(host->clk);
838 writew(div, host->base + JZ_REG_MMC_CLKRT);
844 struct jz4740_mmc_host *host = mmc_priv(mmc);
846 host->req = req;
848 writew(0xffff, host->base + JZ_REG_MMC_IREG);
850 writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
851 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true);
853 host->state = JZ4740_MMC_STATE_READ_RESPONSE;
854 set_bit(0, &host->waiting);
855 mod_timer(&host->timeout_timer, jiffies + 5*HZ);
856 jz4740_mmc_send_command(host, req->cmd);
861 struct jz4740_mmc_host *host = mmc_priv(mmc);
863 jz4740_mmc_set_clock_rate(host, ios->clock);
867 jz4740_mmc_reset(host);
868 if (gpio_is_valid(host->pdata->gpio_power))
869 gpio_set_value(host->pdata->gpio_power,
870 !host->pdata->power_active_low);
871 host->cmdat |= JZ_MMC_CMDAT_INIT;
872 clk_prepare_enable(host->clk);
877 if (gpio_is_valid(host->pdata->gpio_power))
878 gpio_set_value(host->pdata->gpio_power,
879 host->pdata->power_active_low);
880 clk_disable_unprepare(host->clk);
886 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
889 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
898 struct jz4740_mmc_host *host = mmc_priv(mmc);
899 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable);
984 static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host)
987 if (host->pdata && host->pdata->data_1bit)
997 struct jz4740_mmc_host *host;
1004 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
1008 host = mmc_priv(mmc);
1009 host->pdata = pdata;
1011 host->irq = platform_get_irq(pdev, 0);
1012 if (host->irq < 0) {
1013 ret = host->irq;
1018 host->clk = devm_clk_get(&pdev->dev, "mmc");
1019 if (IS_ERR(host->clk)) {
1020 ret = PTR_ERR(host->clk);
1025 host->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1026 host->base = devm_ioremap_resource(&pdev->dev, host->mem_res);
1027 if (IS_ERR(host->base)) {
1028 ret = PTR_ERR(host->base);
1033 ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1057 host->mmc = mmc;
1058 host->pdev = pdev;
1059 spin_lock_init(&host->lock);
1060 host->irq_mask = 0xffff;
1062 ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0,
1063 dev_name(&pdev->dev), host);
1069 jz4740_mmc_reset(host);
1070 jz4740_mmc_clock_disable(host);
1071 setup_timer(&host->timeout_timer, jz4740_mmc_timeout,
1072 (unsigned long)host);
1074 set_timer_slack(&host->timeout_timer, HZ);
1076 host->use_dma = true;
1077 if (host->use_dma && jz4740_mmc_acquire_dma_channels(host) != 0)
1078 host->use_dma = false;
1080 platform_set_drvdata(pdev, host);
1084 dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
1090 host->use_dma ? "DMA" : "PIO",
1096 free_irq(host->irq, host);
1100 if (host->use_dma)
1101 jz4740_mmc_release_dma_channels(host);
1102 jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1111 struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
1113 del_timer_sync(&host->timeout_timer);
1114 jz4740_mmc_set_irq_enabled(host, 0xff, false);
1115 jz4740_mmc_reset(host);
1117 mmc_remove_host(host->mmc);
1119 free_irq(host->irq, host);
1122 jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1124 if (host->use_dma)
1125 jz4740_mmc_release_dma_channels(host);
1127 mmc_free_host(host->mmc);
1136 struct jz4740_mmc_host *host = dev_get_drvdata(dev);
1138 jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1145 struct jz4740_mmc_host *host = dev_get_drvdata(dev);
1147 jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host));