Lines Matching refs:host
2 * linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver
28 #include <linux/mmc/host.h>
67 msmsdcc_disable_clocks(struct msmsdcc_host *host, int deferr)
69 WARN_ON(!host->clks_on);
71 BUG_ON(host->curr.mrq);
74 mod_timer(&host->busclk_timer, jiffies + BUSCLK_TIMEOUT);
76 del_timer_sync(&host->busclk_timer);
80 if (host->clks_on) {
81 clk_disable(host->clk);
82 clk_disable(host->pclk);
83 host->clks_on = 0;
89 msmsdcc_enable_clocks(struct msmsdcc_host *host)
93 del_timer_sync(&host->busclk_timer);
95 if (!host->clks_on) {
96 rc = clk_enable(host->pclk);
99 rc = clk_enable(host->clk);
101 clk_disable(host->pclk);
105 (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
106 host->clks_on = 1;
112 msmsdcc_readl(struct msmsdcc_host *host, unsigned int reg)
114 return readl(host->base + reg);
118 msmsdcc_writel(struct msmsdcc_host *host, u32 data, unsigned int reg)
120 writel(data, host->base + reg);
123 (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
127 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
130 static void msmsdcc_reset_and_restore(struct msmsdcc_host *host)
137 mci_clk = readl(host->base + MMCICLOCK);
138 mci_mask0 = readl(host->base + MMCIMASK0);
141 ret = clk_reset(host->clk, CLK_RESET_ASSERT);
144 mmc_hostname(host->mmc), host->clk_rate, ret);
146 ret = clk_reset(host->clk, CLK_RESET_DEASSERT);
149 mmc_hostname(host->mmc), host->clk_rate, ret);
152 mmc_hostname(host->mmc));
155 writel(host->pwr, host->base + MMCIPOWER);
156 writel(mci_clk, host->base + MMCICLOCK);
157 writel(mci_mask0, host->base + MMCIMASK0);
158 ret = clk_set_rate(host->clk, host->clk_rate);
161 mmc_hostname(host->mmc), host->clk_rate, ret);
165 msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
167 BUG_ON(host->curr.data);
169 host->curr.mrq = NULL;
170 host->curr.cmd = NULL;
173 mrq->data->bytes_xfered = host->curr.data_xfered;
178 msmsdcc_disable_clocks(host, 1);
181 * Need to drop the host lock here; mmc_request_done may call
184 spin_unlock(&host->lock);
185 mmc_request_done(host->mmc, mrq);
186 spin_lock(&host->lock);
190 msmsdcc_stop_data(struct msmsdcc_host *host)
192 host->curr.data = NULL;
193 host->curr.got_dataend = 0;
196 uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host)
198 return host->memres->start + MMCIFIFO;
202 msmsdcc_start_command_exec(struct msmsdcc_host *host, u32 arg, u32 c) {
203 msmsdcc_writel(host, arg, MMCIARGUMENT);
204 msmsdcc_writel(host, c, MMCICOMMAND);
210 struct msmsdcc_host *host = (struct msmsdcc_host *)cmd->data;
212 msmsdcc_writel(host, host->cmd_timeout, MMCIDATATIMER);
213 msmsdcc_writel(host, (unsigned int)host->curr.xfer_size,
215 msmsdcc_writel(host, (msmsdcc_readl(host, MMCIMASK0) &
216 (~MCI_IRQ_PIO)) | host->cmd_pio_irqmask, MMCIMASK0);
217 msmsdcc_writel(host, host->cmd_datactrl, MMCIDATACTRL);
219 if (host->cmd_cmd) {
220 msmsdcc_start_command_exec(host,
221 (u32) host->cmd_cmd->arg,
222 (u32) host->cmd_c);
224 host->dma.active = 1;
230 struct msmsdcc_host *host = (struct msmsdcc_host *)data;
235 spin_lock_irqsave(&host->lock, flags);
236 host->dma.active = 0;
238 err = host->dma.err;
239 mrq = host->curr.mrq;
243 if (!(host->dma.result & DMOV_RSLT_VALID)) {
248 if (host->dma.result & DMOV_RSLT_DONE) {
249 host->curr.data_xfered = host->curr.xfer_size;
252 if (host->dma.result & DMOV_RSLT_ERROR)
254 mmc_hostname(host->mmc), host->dma.result);
255 if (host->dma.result & DMOV_RSLT_FLUSH)
257 mmc_hostname(host->mmc), host->dma.result);
263 msmsdcc_reset_and_restore(host);
267 dma_unmap_sg(mmc_dev(host->mmc), host->dma.sg, host->dma.num_ents,
268 host->dma.dir);
270 host->dma.sg = NULL;
271 host->dma.busy = 0;
273 if (host->curr.got_dataend || mrq->data->error) {
279 msmsdcc_stop_data(host);
282 host->curr.data_xfered = host->curr.xfer_size;
284 host->curr.mrq = NULL;
285 host->curr.cmd = NULL;
286 mrq->data->bytes_xfered = host->curr.data_xfered;
288 spin_unlock_irqrestore(&host->lock, flags);
290 msmsdcc_disable_clocks(host, 1);
292 mmc_request_done(host->mmc, mrq);
295 msmsdcc_start_command(host, mrq->data->stop, 0);
299 spin_unlock_irqrestore(&host->lock, flags);
310 struct msmsdcc_host *host = dma_data->host;
316 tasklet_schedule(&host->dma_tlet);
319 static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data)
321 if (host->dma.channel == -1)
331 static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data)
341 rc = validate_dma(host, data);
345 host->dma.sg = data->sg;
346 host->dma.num_ents = data->sg_len;
348 BUG_ON(host->dma.num_ents > NR_SG); /* Prevent memory corruption */
350 nc = host->dma.nc;
352 switch (host->pdev_id) {
366 host->dma.sg = NULL;
367 host->dma.num_ents = 0;
372 host->dma.dir = DMA_FROM_DEVICE;
374 host->dma.dir = DMA_TO_DEVICE;
376 host->curr.user_pages = 0;
381 BUG_ON(host->dma.cmd_busaddr & 0x07);
383 nc->cmdptr = (host->dma.cmd_busaddr >> 3) | CMD_PTR_LP;
384 host->dma.hdr.cmdptr = DMOV_CMD_PTR_LIST |
385 DMOV_CMD_ADDR(host->dma.cmdptr_busaddr);
386 host->dma.hdr.complete_func = msmsdcc_dma_complete_func;
388 n = dma_map_sg(mmc_dev(host->mmc), host->dma.sg,
389 host->dma.num_ents, host->dma.dir);
392 mmc_hostname(host->mmc));
393 host->dma.sg = NULL;
394 host->dma.num_ents = 0;
398 for_each_sg(host->dma.sg, sg, n, i) {
409 box->src_row_addr = msmsdcc_fifo_addr(host);
420 box->dst_row_addr = msmsdcc_fifo_addr(host);
446 msmsdcc_start_command_deferred(struct msmsdcc_host *host,
465 if (host->prog_scan && (cmd->opcode == 12)) {
467 host->prog_enable = true;
476 if (host->curr.cmd != NULL) {
478 mmc_hostname(host->mmc));
480 host->curr.cmd = cmd;
484 msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data,
491 host->curr.data = data;
492 host->curr.xfer_size = data->blksz * data->blocks;
493 host->curr.xfer_remain = host->curr.xfer_size;
494 host->curr.data_xfered = 0;
495 host->curr.got_dataend = 0;
497 memset(&host->pio, 0, sizeof(host->pio));
501 if (!msmsdcc_config_dma(host, data))
504 host->pio.sg = data->sg;
505 host->pio.sg_len = data->sg_len;
506 host->pio.sg_off = 0;
510 if (host->curr.xfer_remain < MCI_FIFOSIZE)
519 clks = (unsigned long long)data->timeout_ns * host->clk_rate;
525 host->cmd_timeout = timeout;
526 host->cmd_pio_irqmask = pio_irqmask;
527 host->cmd_datactrl = datactrl;
528 host->cmd_cmd = cmd;
530 host->dma.hdr.execute_func = msmsdcc_dma_exec_func;
531 host->dma.hdr.data = (void *)host;
532 host->dma.busy = 1;
535 msmsdcc_start_command_deferred(host, cmd, &c);
536 host->cmd_c = c;
538 msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr);
540 host->prog_scan = true;
542 msmsdcc_writel(host, timeout, MMCIDATATIMER);
544 msmsdcc_writel(host, host->curr.xfer_size, MMCIDATALENGTH);
546 msmsdcc_writel(host, (msmsdcc_readl(host, MMCIMASK0) &
549 msmsdcc_writel(host, datactrl, MMCIDATACTRL);
553 msmsdcc_start_command(host, cmd, c);
559 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c)
564 host->stats.cmds++;
566 msmsdcc_start_command_deferred(host, cmd, &c);
567 msmsdcc_start_command_exec(host, cmd->arg, c);
571 msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data,
575 pr_err("%s: Data CRC error\n", mmc_hostname(host->mmc));
582 pr_err("%s: Data timeout\n", mmc_hostname(host->mmc));
585 pr_err("%s: RX overrun\n", mmc_hostname(host->mmc));
588 pr_err("%s: TX underrun\n", mmc_hostname(host->mmc));
592 mmc_hostname(host->mmc), status);
599 msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain)
607 while (msmsdcc_readl(host, MMCISTATUS) & MCI_RXDATAAVLBL) {
608 *ptr = msmsdcc_readl(host, MMCIFIFO + (count % MCI_FIFOSIZE));
620 msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer,
623 void __iomem *base = host->base;
641 status = msmsdcc_readl(host, MMCISTATUS);
648 msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin)
651 if ((msmsdcc_readl(host, MMCISTATUS) & mask))
662 struct msmsdcc_host *host = dev_id;
666 status = msmsdcc_readl(host, MMCISTATUS);
667 mci_mask0 = msmsdcc_readl(host, MMCIMASK0);
678 if (host->curr.xfer_remain == 0 || !msmsdcc_piopoll)
681 if (msmsdcc_spin_on_status(host,
691 buffer = kmap_atomic(sg_page(host->pio.sg))
692 + host->pio.sg->offset;
693 buffer += host->pio.sg_off;
694 remain = host->pio.sg->length - host->pio.sg_off;
697 len = msmsdcc_pio_read(host, buffer, remain);
699 len = msmsdcc_pio_write(host, buffer, remain, status);
705 host->pio.sg_off += len;
706 host->curr.xfer_remain -= len;
707 host->curr.data_xfered += len;
712 if (status & MCI_RXACTIVE && host->curr.user_pages)
713 flush_dcache_page(sg_page(host->pio.sg));
715 if (!--host->pio.sg_len) {
716 memset(&host->pio, 0, sizeof(host->pio));
721 host->pio.sg++;
722 host->pio.sg_off = 0;
725 status = msmsdcc_readl(host, MMCISTATUS);
728 if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE)
729 msmsdcc_writel(host, (mci_mask0 & (~MCI_IRQ_PIO)) |
732 if (!host->curr.xfer_remain)
733 msmsdcc_writel(host, (mci_mask0 & (~MCI_IRQ_PIO)) | 0,
739 static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
741 struct mmc_command *cmd = host->curr.cmd;
743 host->curr.cmd = NULL;
744 cmd->resp[0] = msmsdcc_readl(host, MMCIRESPONSE0);
745 cmd->resp[1] = msmsdcc_readl(host, MMCIRESPONSE1);
746 cmd->resp[2] = msmsdcc_readl(host, MMCIRESPONSE2);
747 cmd->resp[3] = msmsdcc_readl(host, MMCIRESPONSE3);
753 pr_err("%s: Command CRC error\n", mmc_hostname(host->mmc));
758 if (host->curr.data && host->dma.sg)
759 msm_dmov_stop_cmd(host->dma.channel,
760 &host->dma.hdr, 0);
761 else if (host->curr.data) { /* Non DMA */
762 msmsdcc_reset_and_restore(host);
763 msmsdcc_stop_data(host);
764 msmsdcc_request_end(host, cmd->mrq);
765 } else { /* host->data == NULL */
766 if (!cmd->error && host->prog_enable) {
768 host->prog_scan = false;
769 host->prog_enable = false;
770 msmsdcc_request_end(host, cmd->mrq);
772 host->curr.cmd = cmd;
775 if (host->prog_enable) {
776 host->prog_scan = false;
777 host->prog_enable = false;
779 msmsdcc_request_end(host, cmd->mrq);
784 msmsdcc_start_data(host, cmd->data,
789 msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
792 struct mmc_data *data = host->curr.data;
795 MCI_CMDTIMEOUT | MCI_PROGDONE) && host->curr.cmd) {
796 msmsdcc_do_cmdirq(host, status);
805 msmsdcc_data_err(host, data, status);
806 host->curr.data_xfered = 0;
807 if (host->dma.sg)
808 msm_dmov_stop_cmd(host->dma.channel,
809 &host->dma.hdr, 0);
811 msmsdcc_reset_and_restore(host);
812 if (host->curr.data)
813 msmsdcc_stop_data(host);
815 msmsdcc_request_end(host, data->mrq);
817 msmsdcc_start_command(host, data->stop, 0);
822 if (!host->curr.got_dataend && (status & MCI_DATAEND))
823 host->curr.got_dataend = 1;
828 if (host->curr.got_dataend && !host->dma.busy) {
839 msmsdcc_pio_irq(1, host);
841 msmsdcc_stop_data(host);
843 host->curr.data_xfered = host->curr.xfer_size;
846 msmsdcc_request_end(host, data->mrq);
848 msmsdcc_start_command(host, data->stop, 0);
855 struct msmsdcc_host *host = dev_id;
856 void __iomem *base = host->base;
861 spin_lock(&host->lock);
864 status = msmsdcc_readl(host, MMCISTATUS);
865 status &= msmsdcc_readl(host, MMCIMASK0);
868 msmsdcc_writel(host, status, MMCICLEAR);
876 msmsdcc_handle_irq_data(host, status, base);
885 spin_unlock(&host->lock);
892 mmc_signal_sdio_irq(host->mmc);
900 struct msmsdcc_host *host = mmc_priv(mmc);
903 WARN_ON(host->curr.mrq != NULL);
904 WARN_ON(host->pwr == 0);
906 spin_lock_irqsave(&host->lock, flags);
908 host->stats.reqs++;
910 if (host->eject) {
918 spin_unlock_irqrestore(&host->lock, flags);
923 msmsdcc_enable_clocks(host);
925 host->curr.mrq = mrq;
929 msmsdcc_start_data(host, mrq->data, mrq->cmd, 0);
931 msmsdcc_start_command(host, mrq->cmd, 0);
933 if (host->cmdpoll && !msmsdcc_spin_on_status(host,
936 uint32_t status = msmsdcc_readl(host, MMCISTATUS);
937 msmsdcc_do_cmdirq(host, status);
938 msmsdcc_writel(host,
941 host->stats.cmdpoll_hits++;
943 host->stats.cmdpoll_misses++;
945 spin_unlock_irqrestore(&host->lock, flags);
948 static void msmsdcc_setup_gpio(struct msmsdcc_host *host, bool enable)
953 if (!host->plat->gpio_data || host->gpio_config_status == enable)
956 curr = host->plat->gpio_data;
963 mmc_hostname(host->mmc),
972 host->gpio_config_status = enable;
983 struct msmsdcc_host *host = mmc_priv(mmc);
988 spin_lock_irqsave(&host->lock, flags);
990 msmsdcc_enable_clocks(host);
992 spin_unlock_irqrestore(&host->lock, flags);
995 if (ios->clock != host->clk_rate) {
996 rc = clk_set_rate(host->clk, ios->clock);
999 mmc_hostname(host->mmc), rc);
1001 host->clk_rate = ios->clock;
1015 if (host->plat->translate_vdd)
1016 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
1020 msmsdcc_setup_gpio(host, false);
1024 msmsdcc_setup_gpio(host, true);
1034 msmsdcc_writel(host, clk, MMCICLOCK);
1036 if (host->pwr != pwr) {
1037 host->pwr = pwr;
1038 msmsdcc_writel(host, pwr, MMCIPOWER);
1041 spin_lock_irqsave(&host->lock, flags);
1042 msmsdcc_disable_clocks(host, 1);
1043 spin_unlock_irqrestore(&host->lock, flags);
1049 struct msmsdcc_host *host = mmc_priv(mmc);
1053 spin_lock_irqsave(&host->lock, flags);
1055 status = msmsdcc_readl(host, MMCIMASK0);
1060 host->saved_irq0mask = status;
1061 msmsdcc_writel(host, status, MMCIMASK0);
1063 spin_unlock_irqrestore(&host->lock, flags);
1068 struct msmsdcc_host *host = mmc_priv(mmc);
1070 if (host->plat->init_card)
1071 host->plat->init_card(card);
1084 struct msmsdcc_host *host = (struct msmsdcc_host *)data;
1087 if (!host->plat->status) {
1088 mmc_detect_change(host->mmc, 0);
1092 status = host->plat->status(mmc_dev(host->mmc));
1093 host->eject = !status;
1094 if (status ^ host->oldstat) {
1096 mmc_hostname(host->mmc), host->oldstat, status);
1098 mmc_detect_change(host->mmc, (5 * HZ) / 2);
1100 mmc_detect_change(host->mmc, 0);
1103 host->oldstat = status;
1106 if (host->timer.function)
1107 mod_timer(&host->timer, jiffies + HZ);
1113 struct msmsdcc_host *host = dev_id;
1116 msmsdcc_check_status((unsigned long) host);
1123 struct msmsdcc_host *host = dev_id;
1125 pr_debug("%s: card_present %d\n", mmc_hostname(host->mmc),
1127 msmsdcc_check_status((unsigned long) host);
1133 struct msmsdcc_host *host = (struct msmsdcc_host *) _data;
1135 if (host->clks_on)
1136 msmsdcc_disable_clocks(host, 0);
1140 msmsdcc_init_dma(struct msmsdcc_host *host)
1142 memset(&host->dma, 0, sizeof(struct msmsdcc_dma_data));
1143 host->dma.host = host;
1144 host->dma.channel = -1;
1146 if (!host->dmares)
1149 host->dma.nc = dma_alloc_coherent(NULL,
1151 &host->dma.nc_busaddr,
1153 if (host->dma.nc == NULL) {
1157 memset(host->dma.nc, 0x00, sizeof(struct msmsdcc_nc_dmadata));
1158 host->dma.cmd_busaddr = host->dma.nc_busaddr;
1159 host->dma.cmdptr_busaddr = host->dma.nc_busaddr +
1161 host->dma.channel = host->dmares->start;
1170 struct msmsdcc_host *host;
1206 * Setup our host structure
1215 host = mmc_priv(mmc);
1216 host->pdev_id = pdev->id;
1217 host->plat = plat;
1218 host->mmc = mmc;
1219 host->curr.cmd = NULL;
1220 init_timer(&host->busclk_timer);
1221 host->busclk_timer.data = (unsigned long) host;
1222 host->busclk_timer.function = msmsdcc_busclk_expired;
1225 host->cmdpoll = 1;
1227 host->base = ioremap(memres->start, PAGE_SIZE);
1228 if (!host->base) {
1233 host->cmd_irqres = cmd_irqres;
1234 host->memres = memres;
1235 host->dmares = dmares;
1236 spin_lock_init(&host->lock);
1238 tasklet_init(&host->dma_tlet, msmsdcc_dma_complete_tlet,
1239 (unsigned long)host);
1244 if (host->dmares) {
1245 ret = msmsdcc_init_dma(host);
1249 host->dma.channel = -1;
1253 host->pclk = clk_get(&pdev->dev, "sdc_pclk");
1254 if (IS_ERR(host->pclk)) {
1255 ret = PTR_ERR(host->pclk);
1259 host->clk = clk_get(&pdev->dev, "sdc_clk");
1260 if (IS_ERR(host->clk)) {
1261 ret = PTR_ERR(host->clk);
1265 ret = clk_set_rate(host->clk, msmsdcc_fmin);
1271 ret = clk_prepare(host->pclk);
1275 ret = clk_prepare(host->clk);
1280 ret = msmsdcc_enable_clocks(host);
1284 host->pclk_rate = clk_get_rate(host->pclk);
1285 host->clk_rate = clk_get_rate(host->clk);
1288 * Setup MMC host structure
1308 msmsdcc_writel(host, 0, MMCIMASK0);
1309 msmsdcc_writel(host, 0x5e007ff, MMCICLEAR);
1311 msmsdcc_writel(host, MCI_IRQENABLE, MMCIMASK0);
1312 host->saved_irq0mask = MCI_IRQENABLE;
1318 memset(&host->timer, 0, sizeof(host->timer));
1324 host->stat_irq = stat_irqres->start;
1325 ret = request_irq(host->stat_irq,
1329 host);
1332 mmc_hostname(mmc), host->stat_irq, ret);
1336 plat->register_status_notify(msmsdcc_status_notify_cb, host);
1341 init_timer(&host->timer);
1342 host->timer.data = (unsigned long)host;
1343 host->timer.function = msmsdcc_check_status;
1344 host->timer.expires = jiffies + HZ;
1345 add_timer(&host->timer);
1349 host->oldstat = host->plat->status(mmc_dev(host->mmc));
1350 host->eject = !host->oldstat;
1354 DRIVER_NAME " (cmd)", host);
1359 DRIVER_NAME " (pio)", host);
1369 (unsigned int) host->stat_irq, host->dma.channel);
1373 mmc_hostname(mmc), msmsdcc_fmin, msmsdcc_fmax, host->pclk_rate);
1374 pr_info("%s: Slot eject status = %d\n", mmc_hostname(mmc), host->eject);
1378 if (host->dma.channel != -1) {
1380 mmc_hostname(mmc), host->dma.nc, host->dma.nc_busaddr);
1382 mmc_hostname(mmc), host->dma.cmd_busaddr,
1383 host->dma.cmdptr_busaddr);
1386 if (host->timer.function)
1391 free_irq(cmd_irqres->start, host);
1393 if (host->stat_irq)
1394 free_irq(host->stat_irq, host);
1396 msmsdcc_disable_clocks(host, 0);
1398 clk_unprepare(host->clk);
1400 clk_unprepare(host->pclk);
1402 clk_put(host->clk);
1404 clk_put(host->pclk);
1406 if (host->dmares)
1408 host->dma.nc, host->dma.nc_busaddr);
1410 tasklet_kill(&host->dma_tlet);
1411 iounmap(host->base);
1425 struct msmsdcc_host *host = mmc_priv(mmc);
1427 if (host->stat_irq)
1428 disable_irq(host->stat_irq);
1430 msmsdcc_writel(host, 0, MMCIMASK0);
1431 if (host->clks_on)
1432 msmsdcc_disable_clocks(host, 0);
1443 struct msmsdcc_host *host = mmc_priv(mmc);
1445 msmsdcc_enable_clocks(host);
1447 msmsdcc_writel(host, host->saved_irq0mask, MMCIMASK0);
1449 if (host->stat_irq)
1450 enable_irq(host->stat_irq);
1452 msmsdcc_disable_clocks(host, 1);