Cross Reference: /drivers/mmc/host/sdhci-esdhc-imx.c

Lines Matching refs:host
21 #include <linux/mmc/host.h>
213 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
215 	void __iomem *base = host->ioaddr + (reg & ~0x3);
221 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
223 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
225 	u32 val = readl(host->ioaddr + reg);
258 				val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
287 			writel(SDHCI_INT_RESPONSE, host->ioaddr +
296 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
298 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
312 			data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
314 			writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
316 			writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
324 			v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
326 			writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
333 				writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
345 	writel(val, host->ioaddr + reg);
348 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
350 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
359 			 * The usdhc register returns a wrong host version.
367 		val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
373 				val = readl(host->ioaddr + ESDHC_MIX_CTRL);
376 				val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
391 			u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
399 			ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
405 	return readw(host->ioaddr + reg);
408 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
410 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
416 		new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
421 			writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
424 		new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
429 		writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
431 			new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
436 			writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
438 			u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
439 			u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
454 			writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
455 			writel(m, host->ioaddr + ESDHC_MIX_CTRL);
460 				&& (host->cmd->opcode == SD_IO_RW_EXTENDED)
461 				&& (host->cmd->data->blocks > 1)
462 				&& (host->cmd->data->flags & MMC_DATA_READ)) {
464 			v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
466 			writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
470 			u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
477 			writel(m, host->ioaddr + ESDHC_MIX_CTRL);
487 		if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
490 		if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
496 			       host->ioaddr + SDHCI_TRANSFER_MODE);
499 			       host->ioaddr + SDHCI_TRANSFER_MODE);
505 	esdhc_clrset_le(host, 0xffff, val, reg);
508 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
510 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
541 		esdhc_clrset_le(host, mask, new_val, reg);
544 	esdhc_clrset_le(host, 0xff, val, reg);
555 		esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
562 			new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
564 					host->ioaddr + ESDHC_MIX_CTRL);
570 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
572 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
582 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
584 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
589 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
592 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
600 		host->mmc->actual_clock = 0;
603 			val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
605 					host->ioaddr + ESDHC_VENDOR_SPEC);
613 	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
616 	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
624 	host->mmc->actual_clock = host_clock / pre_div / div;
625 	dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
626 		clock, host->mmc->actual_clock);
634 	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
638 	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
641 		val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
643 		host->ioaddr + ESDHC_VENDOR_SPEC);
649 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
651 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
657 		return mmc_gpio_get_ro(host->mmc);
659 		return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
668 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
684 	esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
688 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
696 	pm_runtime_get_sync(host->mmc->parent);
697 	reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
700 	writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
701 	writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
702 	dev_dbg(mmc_dev(host->mmc),
704 			val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
712 static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode,
738 	spin_lock_irq(&host->lock);
739 	host->mrq = &mrq;
741 	sdhci_send_command(host, mrq.cmd);
743 	spin_unlock_irq(&host->lock);
755 static void esdhc_post_tuning(struct sdhci_host *host)
759 	reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
761 	writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
764 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
779 		esdhc_prepare_tuning(host, min);
780 		if (!esdhc_send_tuning_cmd(host, opcode, &sg))
788 		esdhc_prepare_tuning(host, max);
789 		if (esdhc_send_tuning_cmd(host, opcode, &sg)) {
798 	esdhc_prepare_tuning(host, avg);
799 	ret = esdhc_send_tuning_cmd(host, opcode, &sg);
800 	esdhc_post_tuning(host);
804 	dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
810 static int esdhc_change_pinstate(struct sdhci_host *host,
813 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
817 	dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
841 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
843 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
856 		writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |
858 				host->ioaddr + ESDHC_MIX_CTRL);
867 			writel(v, host->ioaddr + ESDHC_DLL_CTRL);
872 	esdhc_change_pinstate(host, timing);
875 static void esdhc_reset(struct sdhci_host *host, u8 mask)
877 	sdhci_reset(host, mask);
879 	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
880 	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
883 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
885 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
891 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
893 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
897 	sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
981 	struct sdhci_host *host;
986 	host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
987 	if (IS_ERR(host))
988 		return PTR_ERR(host);
990 	pltfm_host = sdhci_priv(host);
1036 		dev_err(mmc_dev(host->mmc), "could not get default state\n");
1040 	host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1044 		host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
1052 		writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
1053 		host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1054 		host->mmc->caps |= MMC_CAP_1_8V_DDR;
1062 		writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
1064 			host->ioaddr + ESDHC_TUNING_CTRL);
1068 		if (!host->mmc->parent->platform_data) {
1069 			dev_err(mmc_dev(host->mmc), "no board data!\n");
1074 					host->mmc->parent->platform_data);
1079 		err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1081 			dev_err(mmc_dev(host->mmc),
1085 		host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1091 		err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1093 			dev_err(mmc_dev(host->mmc),
1101 		host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1105 		host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1114 		host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1117 		host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1121 		host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1133 			dev_warn(mmc_dev(host->mmc),
1136 			host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1139 		host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1142 	err = sdhci_add_host(host);
1165 	struct sdhci_host *host = platform_get_drvdata(pdev);
1166 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1168 	int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1170 	sdhci_remove_host(host, dead);
1189 	struct sdhci_host *host = dev_get_drvdata(dev);
1190 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1194 	ret = sdhci_runtime_suspend_host(host);
1196 	if (!sdhci_sdio_irq_enabled(host)) {
1207 	struct sdhci_host *host = dev_get_drvdata(dev);
1208 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1211 	if (!sdhci_sdio_irq_enabled(host)) {
1217 	return sdhci_runtime_resume_host(host);