Cross Reference: /drivers/mmc/host/wmt-sdmmc.c

Lines Matching defs:reg_tmp
216 	u32 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
219 		reg_tmp &= ~BM_SD_OFF;
221 		reg_tmp |= BM_SD_OFF;
223 	writeb(reg_tmp, priv->sdmmc_base + SDMMC_BUSMODE);
251 	u32 reg_tmp;
253 	reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
254 	writeb(reg_tmp | CTLR_CMD_START, priv->sdmmc_base + SDMMC_CTLR);
261 	u32 reg_tmp;
271 	reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
272 	writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR);
284 	reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
285 	writeb((reg_tmp & 0x0F) | (cmdtype << 4),
379 	u32 reg_tmp;
389 	reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0);
390 	if ((reg_tmp & INT0_DI_INT_EN) && (status0 & STS0_DEVICE_INS)) {
468 	u32 reg_tmp;
473 	reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
474 	writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE);
477 	reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
478 	writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR);
497 	reg_tmp = readb(priv->sdmmc_base + SDMMC_STS2);
498 	writeb(reg_tmp | STS2_DIS_FORCECLK, priv->sdmmc_base + SDMMC_STS2);
531 	u32 reg_tmp;
544 		reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
545 		writel(reg_tmp & DMA_CCR_IF_TO_PERIPHERAL, priv->sdmmc_base +
548 		reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
549 		writel(reg_tmp | DMA_CCR_PERIPHERAL_TO_IF, priv->sdmmc_base +
556 	u32 reg_tmp;
558 	reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
559 	writel(reg_tmp | DMA_CCR_RUN, priv->sdmmc_base + SDDMA_CCR);
570 	u32 reg_tmp;
613 		reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
614 		writew((reg_tmp & 0xF800) | (req->data->blksz - 1),
885 	u32 reg_tmp;
891 	reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
892 	writel(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE);
893 	reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
894 	writew(reg_tmp & ~(0xA000), priv->sdmmc_base + SDMMC_BLKLEN);
925 	u32 reg_tmp;
934 	reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
935 	writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base +
938 	reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
939 	writew(reg_tmp & 0x5FFF, priv->sdmmc_base + SDMMC_BLKLEN);
950 	u32 reg_tmp;
959 		reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
960 		writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base +
963 		reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
964 		writew(reg_tmp | (BLKL_GPI_CD | BLKL_INT_ENABLE),
967 		reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0);
968 		writeb(reg_tmp | INT0_DI_INT_EN, priv->sdmmc_base +