Lines Matching refs:host
228 static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
233 writel(MLCCMD_RESET, MLC_CMD(host->io_base));
237 clkrate = clk_get_rate(host->clk);
243 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
247 writel(tmp, MLC_ICR(host->io_base));
251 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
255 tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1);
256 tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1);
257 tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1);
258 tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1);
259 tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low);
260 tmp |= MLCTIMEREG_WR_HIGH(clkrate / host->ncfg->wr_high + 1);
261 tmp |= MLCTIMEREG_WR_LOW(clkrate / host->ncfg->wr_low);
262 writel(tmp, MLC_TIME_REG(host->io_base));
266 MLC_IRQ_MR(host->io_base));
269 writel(MLCCEH_NORMAL, MLC_CEH(host->io_base));
279 struct lpc32xx_nand_host *host = nand_chip->priv;
283 writel(cmd, MLC_CMD(host->io_base));
285 writel(cmd, MLC_ADDR(host->io_base));
295 struct lpc32xx_nand_host *host = nand_chip->priv;
297 if ((readb(MLC_ISR(host->io_base)) &
305 static irqreturn_t lpc3xxx_nand_irq(int irq, struct lpc32xx_nand_host *host)
310 sr = readb(MLC_IRQ_SR(host->io_base));
312 complete(&host->comp_nand);
314 complete(&host->comp_controller);
321 struct lpc32xx_nand_host *host = chip->priv;
323 if (readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)
326 wait_for_completion(&host->comp_nand);
328 while (!(readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)) {
341 struct lpc32xx_nand_host *host = chip->priv;
343 if (readb(MLC_ISR(host->io_base)) & MLCISR_CONTROLLER_READY)
346 wait_for_completion(&host->comp_controller);
348 while (!(readb(MLC_ISR(host->io_base)) &
369 static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
371 if (gpio_is_valid(host->ncfg->wp_gpio))
372 gpio_set_value(host->ncfg->wp_gpio, 0);
378 static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
380 if (gpio_is_valid(host->ncfg->wp_gpio))
381 gpio_set_value(host->ncfg->wp_gpio, 1);
393 struct lpc32xx_nand_host *host = chip->priv;
398 sg_init_one(&host->sgl, mem, len);
400 res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
406 desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
413 init_completion(&host->comp_dma);
415 desc->callback_param = &host->comp_dma;
418 dma_async_issue_pending(host->dma_chan);
420 wait_for_completion_timeout(&host->comp_dma, msecs_to_jiffies(1000));
422 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
426 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
434 struct lpc32xx_nand_host *host = chip->priv;
446 dma_buf = host->dma_buf;
454 for (i = 0; i < host->mlcsubpages; i++) {
456 writeb(0x00, MLC_ECC_AUTO_DEC_REG(host->io_base));
462 mlc_isr = readl(MLC_ISR(host->io_base));
479 readl(MLC_BUFF(host->io_base));
485 readl(MLC_BUFF(host->io_base));
500 struct lpc32xx_nand_host *host = chip->priv;
507 dma_buf = host->dma_buf;
511 for (i = 0; i < host->mlcsubpages; i++) {
513 writeb(0x00, MLC_ECC_ENC_REG(host->io_base));
524 MLC_BUFF(host->io_base));
528 writel(*((uint32_t *)(oobbuf)), MLC_BUFF(host->io_base));
530 writew(*((uint16_t *)(oobbuf)), MLC_BUFF(host->io_base));
534 writeb(0x00, MLC_ECC_AUTO_ENC_REG(host->io_base));
545 struct lpc32xx_nand_host *host = chip->priv;
548 lpc32xx_read_page(mtd, chip, host->dummy_buf, 1, page);
566 static int lpc32xx_dma_setup(struct lpc32xx_nand_host *host)
568 struct mtd_info *mtd = &host->mtd;
571 if (!host->pdata || !host->pdata->dma_filter) {
578 host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
580 if (!host->dma_chan) {
590 host->dma_slave_config.direction = DMA_DEV_TO_MEM;
591 host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
592 host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
593 host->dma_slave_config.src_maxburst = 128;
594 host->dma_slave_config.dst_maxburst = 128;
596 host->dma_slave_config.device_fc = false;
597 host->dma_slave_config.src_addr = MLC_BUFF(host->io_base_phy);
598 host->dma_slave_config.dst_addr = MLC_BUFF(host->io_base_phy);
599 if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
606 dma_release_channel(host->dma_chan);
644 struct lpc32xx_nand_host *host;
652 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
653 if (!host)
657 host->io_base = devm_ioremap_resource(&pdev->dev, rc);
658 if (IS_ERR(host->io_base))
659 return PTR_ERR(host->io_base);
661 host->io_base_phy = rc->start;
663 mtd = &host->mtd;
664 nand_chip = &host->nand_chip;
666 host->ncfg = lpc32xx_parse_dt(&pdev->dev);
667 if (!host->ncfg) {
672 if (host->ncfg->wp_gpio == -EPROBE_DEFER)
674 if (gpio_is_valid(host->ncfg->wp_gpio) &&
675 gpio_request(host->ncfg->wp_gpio, "NAND WP")) {
679 lpc32xx_wp_disable(host);
681 host->pdata = dev_get_platdata(&pdev->dev);
683 nand_chip->priv = host; /* link the private data structures */
689 host->clk = clk_get(&pdev->dev, NULL);
690 if (IS_ERR(host->clk)) {
695 clk_enable(host->clk);
700 nand_chip->IO_ADDR_R = MLC_DATA(host->io_base);
701 nand_chip->IO_ADDR_W = MLC_DATA(host->io_base);
704 lpc32xx_nand_setup(host);
706 platform_set_drvdata(pdev, host);
725 res = lpc32xx_dma_setup(host);
741 host->dma_buf = devm_kzalloc(&pdev->dev, mtd->writesize, GFP_KERNEL);
742 if (!host->dma_buf) {
747 host->dummy_buf = devm_kzalloc(&pdev->dev, mtd->writesize, GFP_KERNEL);
748 if (!host->dummy_buf) {
756 host->mlcsubpages = mtd->writesize / 512;
759 readb(MLC_IRQ_SR(host->io_base));
761 init_completion(&host->comp_nand);
762 init_completion(&host->comp_controller);
764 host->irq = platform_get_irq(pdev, 0);
765 if ((host->irq < 0) || (host->irq >= NR_IRQS)) {
771 if (request_irq(host->irq, (irq_handler_t)&lpc3xxx_nand_irq,
772 IRQF_TRIGGER_HIGH, DRV_NAME, host)) {
790 res = mtd_device_parse_register(mtd, NULL, &ppdata, host->ncfg->parts,
791 host->ncfg->num_parts);
798 free_irq(host->irq, host);
801 dma_release_channel(host->dma_chan);
803 clk_disable(host->clk);
804 clk_put(host->clk);
806 lpc32xx_wp_enable(host);
807 gpio_free(host->ncfg->wp_gpio);
817 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
818 struct mtd_info *mtd = &host->mtd;
821 free_irq(host->irq, host);
823 dma_release_channel(host->dma_chan);
825 clk_disable(host->clk);
826 clk_put(host->clk);
828 lpc32xx_wp_enable(host);
829 gpio_free(host->ncfg->wp_gpio);
837 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
840 clk_enable(host->clk);
843 lpc32xx_nand_setup(host);
846 lpc32xx_wp_disable(host);
853 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
856 lpc32xx_wp_enable(host);
859 clk_disable(host->clk);