Lines Matching refs:port
110 /* Configure the upstream port, and configure the upstream
111 * port as the port to which ingress and egress monitor frames
122 * 01:80:c2:00:00:2x to the CPU port.
127 * 01:80:c2:00:00:0x to the CPU port.
165 /* Initialise cross-chip port VLAN table to reset defaults. */
184 * ports, but force the CPU port and all DSA ports to 1000 Mb/s
192 /* Do not limit the period of time that this port can be
194 * this port can pause the remote end.
209 * If this is the upstream port for this switch, enable
226 * CPU port, enable learn messages to be sent to this port.
230 /* Port based VLAN map: give each port its own address
231 * database, allow the CPU port to talk to each of the 'real'
233 * the upstream port.
250 * on this port, do a destination address lookup on all
252 * send a copy of all transmitted/received frames on this port
265 * a port bitmap that has only the bit for this port set and
271 * database entries that this port is allowed to use.
322 static int mv88e6123_61_65_port_to_phy_addr(int port)
324 if (port >= 0 && port <= 4)
325 return port;
330 mv88e6123_61_65_phy_read(struct dsa_switch *ds, int port, int regnum)
332 int addr = mv88e6123_61_65_port_to_phy_addr(port);
338 int port, int regnum, u16 val)
340 int addr = mv88e6123_61_65_port_to_phy_addr(port);
378 mv88e6123_61_65_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
381 mv88e6123_61_65_hw_stats, port, data);
386 int port, uint64_t *data)
389 mv88e6123_61_65_hw_stats, port, data);