Lines Matching refs:ret
30 int ret;
34 ret = mdiobus_read(bus, sw_addr, 0);
35 if (ret < 0)
36 return ret;
38 if ((ret & 0x8000) == 0)
47 int ret;
53 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
54 if (ret < 0)
55 return ret;
58 ret = mdiobus_write(bus, sw_addr, 0, 0x9800 | (addr << 5) | reg);
59 if (ret < 0)
60 return ret;
63 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
64 if (ret < 0)
65 return ret;
68 ret = mdiobus_read(bus, sw_addr, 1);
69 if (ret < 0)
70 return ret;
72 return ret & 0xffff;
79 int ret;
85 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
88 return ret;
94 int ret;
100 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
101 if (ret < 0)
102 return ret;
105 ret = mdiobus_write(bus, sw_addr, 1, val);
106 if (ret < 0)
107 return ret;
110 ret = mdiobus_write(bus, sw_addr, 0, 0x9400 | (addr << 5) | reg);
111 if (ret < 0)
112 return ret;
115 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
116 if (ret < 0)
117 return ret;
126 int ret;
132 ret = __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
135 return ret;
168 int ret;
178 ret = REG_READ(REG_GLOBAL2, 0x0d);
179 if ((ret & 0x8000) == 0)
206 int ret;
209 ret = REG_READ(REG_GLOBAL, 0x04);
210 REG_WRITE(REG_GLOBAL, 0x04, ret & ~0x4000);
214 ret = REG_READ(REG_GLOBAL, 0x00);
216 if ((ret & 0xc000) != 0xc000)
225 int ret;
228 ret = REG_READ(REG_GLOBAL, 0x04);
229 REG_WRITE(REG_GLOBAL, 0x04, ret | 0x4000);
233 ret = REG_READ(REG_GLOBAL, 0x00);
235 if ((ret & 0xc000) == 0xc000)
266 int ret;
276 ret = mv88e6xxx_ppu_disable(ds);
277 if (ret < 0) {
279 return ret;
284 ret = 0;
287 return ret;
312 int ret;
314 ret = mv88e6xxx_ppu_access_get(ds);
315 if (ret >= 0) {
316 ret = mv88e6xxx_reg_read(ds, addr, regnum);
320 return ret;
326 int ret;
328 ret = mv88e6xxx_ppu_access_get(ds);
329 if (ret >= 0) {
330 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
334 return ret;
401 int ret;
405 ret = REG_READ(REG_GLOBAL, 0x1d);
406 if ((ret & 0x8000) == 0)
415 int ret;
421 ret = mv88e6xxx_stats_wait(ds);
422 if (ret < 0)
423 return ret;
431 int ret;
435 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x1d, 0xcc00 | stat);
436 if (ret < 0)
439 ret = mv88e6xxx_stats_wait(ds);
440 if (ret < 0)
443 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1e);
444 if (ret < 0)
447 _val = ret << 16;
449 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1f);
450 if (ret < 0)
453 *val = _val | ret;
473 int ret;
478 ret = mv88e6xxx_stats_snapshot(ds, port);
479 if (ret < 0) {