Cross Reference: /drivers/net/ethernet/amd/7990.c

Lines Matching refs:lp
44 #define WRITERAP(lp, x)	out_be16(lp->base + LANCE_RAP, (x))
45 #define WRITERDP(lp, x)	out_be16(lp->base + LANCE_RDP, (x))
46 #define READRDP(lp)	in_be16(lp->base + LANCE_RDP)
58 #define WRITERAP(lp, x)	(lp->writerap(lp, x))
59 #define WRITERDP(lp, x)	(lp->writerdp(lp, x))
60 #define READRDP(lp)	(lp->readrdp(lp))
65 static inline void WRITERAP(struct lance_private *lp, __u16 value)
68 		out_be16(lp->base + HPLANCE_REGOFF + LANCE_RAP, value);
69 	} while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
72 static inline void WRITERDP(struct lance_private *lp, __u16 value)
75 		out_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP, value);
76 	} while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
79 static inline __u16 READRDP(struct lance_private *lp)
83 		value = in_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP);
84 	} while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
115 static void load_csrs(struct lance_private *lp)
117 	volatile struct lance_init_block *aib = lp->lance_init_block;
122 	WRITERAP(lp, LE_CSR1);                    /* load address of init block */
123 	WRITERDP(lp, leptr & 0xFFFF);
124 	WRITERAP(lp, LE_CSR2);
125 	WRITERDP(lp, leptr >> 16);
126 	WRITERAP(lp, LE_CSR3);
127 	WRITERDP(lp, lp->busmaster_regval);       /* set byteswap/ALEctrl/byte ctrl */
130 	WRITERAP(lp, LE_CSR0);
138 	struct lance_private *lp = netdev_priv(dev);
139 	volatile struct lance_init_block *ib = lp->init_block;
144 	aib = lp->lance_init_block;
146 	lp->rx_new = lp->tx_new = 0;
147 	lp->rx_old = lp->tx_old = 0;
176 	lp->tx_full = 0;
178 	for (i = 0; i < (1 << lp->lance_log_tx_bufs); i++) {
192 	for (i = 0; i < (1 << lp->lance_log_rx_bufs); i++) {
209 	ib->rx_len = (lp->lance_log_rx_bufs << 13) | (leptr >> 16);
216 	ib->tx_len = (lp->lance_log_tx_bufs << 13) | (leptr >> 16);
228 static int init_restart_lance(struct lance_private *lp)
232 	WRITERAP(lp, LE_CSR0);
233 	WRITERDP(lp, LE_C0_INIT);
238 	for (i = 0; (i < 100) && !(READRDP(lp) & (LE_C0_ERR | LE_C0_IDON)); i++)
240 	if ((i == 100) || (READRDP(lp) & LE_C0_ERR)) {
241 		printk("LANCE unopened after %d ticks, csr0=%4.4x.\n", i, READRDP(lp));
246 	WRITERDP(lp, LE_C0_IDON);
247 	WRITERDP(lp, LE_C0_INEA | LE_C0_STRT);
254 	struct lance_private *lp = netdev_priv(dev);
258 	WRITERAP(lp, LE_CSR0);
259 	WRITERDP(lp, LE_C0_STOP);
261 	load_csrs(lp);
264 	status = init_restart_lance(lp);
273 	struct lance_private *lp = netdev_priv(dev);
274 	volatile struct lance_init_block *ib = lp->init_block;
284 		if (i == lp->rx_new)
296 	WRITERDP(lp, LE_C0_RINT | LE_C0_INEA);     /* ack Rx int, reenable ints */
297 	for (rd = &ib->brx_ring[lp->rx_new];     /* For each Rx ring we own... */
299 	     rd = &ib->brx_ring[lp->rx_new]) {
328 				lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
335 					 (unsigned char *)&(ib->rx_buf[lp->rx_new][0]),
346 		lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
353 	struct lance_private *lp = netdev_priv(dev);
354 	volatile struct lance_init_block *ib = lp->init_block;
363 	WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
366 	j = lp->tx_old;
367 	for (i = j; i != lp->tx_new; i = j) {
385 				if (lp->auto_select) {
386 					lp->tpe = 1 - lp->tpe;
389 					       lp->tpe ? "TPE" : "AUI");
391 					WRITERAP(lp, LE_CSR0);
392 					WRITERDP(lp, LE_C0_STOP);
394 					load_csrs(lp);
395 					init_restart_lance(lp);
408 				WRITERAP(lp, LE_CSR0);
409 				WRITERDP(lp, LE_C0_STOP);
411 				load_csrs(lp);
412 				init_restart_lance(lp);
432 		j = (j + 1) & lp->tx_ring_mod_mask;
434 	lp->tx_old = j;
435 	WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
443 	struct lance_private *lp = netdev_priv(dev);
446 	spin_lock(&lp->devlock);
448 	WRITERAP(lp, LE_CSR0);              /* LANCE Controller Status */
449 	csr0 = READRDP(lp);
454 		spin_unlock(&lp->devlock);
459 	WRITERDP(lp, csr0 & ~(LE_C0_INEA|LE_C0_TDMD|LE_C0_STOP|LE_C0_STRT|LE_C0_INIT));
463 		WRITERDP(lp, LE_C0_BABL|LE_C0_ERR|LE_C0_MISS|LE_C0_INEA);
481 		WRITERDP(lp, LE_C0_STRT);
484 	if (lp->tx_full && netif_queue_stopped(dev) && (TX_BUFFS_AVAIL >= 0)) {
485 		lp->tx_full = 0;
489 	WRITERAP(lp, LE_CSR0);
490 	WRITERDP(lp, LE_C0_BABL|LE_C0_CERR|LE_C0_MISS|LE_C0_MERR|LE_C0_IDON|LE_C0_INEA);
492 	spin_unlock(&lp->devlock);
498 	struct lance_private *lp = netdev_priv(dev);
502 	if (request_irq(lp->irq, lance_interrupt, IRQF_SHARED, lp->name, dev))
506 	spin_lock_init(&lp->devlock);
515 	struct lance_private *lp = netdev_priv(dev);
520 	WRITERAP(lp, LE_CSR0);
521 	WRITERDP(lp, LE_C0_STOP);
523 	free_irq(lp->irq, dev);
540 	struct lance_private *lp = netdev_priv(dev);
541 	volatile struct lance_init_block *ib = lp->init_block;
566 	entry = lp->tx_new & lp->tx_ring_mod_mask;
576 	lp->tx_new = (lp->tx_new + 1) & lp->tx_ring_mod_mask;
580 	WRITERDP(lp, LE_C0_INEA | LE_C0_TDMD);
583 	spin_lock_irqsave(&lp->devlock, flags);
587 		lp->tx_full = 1;
588 	spin_unlock_irqrestore(&lp->devlock, flags);
597 	struct lance_private *lp = netdev_priv(dev);
598 	volatile struct lance_init_block *ib = lp->init_block;
624 	struct lance_private *lp = netdev_priv(dev);
625 	volatile struct lance_init_block *ib = lp->init_block;
632 	while (lp->tx_old != lp->tx_new)
635 	WRITERAP(lp, LE_CSR0);
636 	WRITERDP(lp, LE_C0_STOP);
645 	load_csrs(lp);
646 	init_restart_lance(lp);
656 	struct lance_private *lp = netdev_priv(dev);
658 	spin_lock(&lp->devlock);
659 	WRITERAP(lp, LE_CSR0);
660 	WRITERDP(lp, LE_C0_STRT);
661 	spin_unlock(&lp->devlock);