Lines Matching refs:port
271 port_mb[params->port].link_status));
351 eee_status[params->port]));
535 const u8 port = params->port;
539 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
541 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
543 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
545 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
547 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
549 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
552 if (!port) {
573 const u8 port = params->port;
580 if (port) {
590 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
595 if (port) {
613 if (port)
618 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
622 * for here is note appropriate.In 2 port mode port0 only COS0-5
624 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
627 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
629 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
631 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
633 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
635 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
637 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
639 if (!port) {
659 const u8 port = params->port;
663 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
664 * port mode port1 has COS0-2 that can be used for WFQ.
666 if (!port) {
689 const u8 port = params->port;
699 if (port)
707 if (port)
714 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
718 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
721 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
723 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
724 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
726 if (!port) {
796 const u8 port = params->port;
802 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
805 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
808 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
812 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
830 const u8 port)
841 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
843 pbf_reg_adress_crd_weight = (port) ?
847 nig_reg_adress_crd_weight = (port) ?
850 pbf_reg_adress_crd_weight = (port) ?
854 nig_reg_adress_crd_weight = (port) ?
858 pbf_reg_adress_crd_weight = (port) ?
862 if (port)
870 if (port)
877 if (port)
962 const u8 port = params->port;
963 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1044 const u8 port = params->port;
1050 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1107 if (port) {
1138 const u8 port = params->port;
1145 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1190 port);
1362 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1461 /* Check 4-port override enabled */
1464 /* Return 4-port mode override value */
1467 /* Return 4-port mode from input pin */
1476 u8 port = params->port;
1477 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1482 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1485 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1522 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1524 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1526 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1532 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1536 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1553 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1557 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1561 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1566 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1653 /* In 4-port mode, need to set the mode only once, so if XMAC is
1666 "XMAC already out of reset in 4-port mode\n");
1690 "Init XMAC to 10G x 1 port per path\n");
1712 u8 port = params->port;
1714 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1728 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1745 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1756 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1812 u8 port = params->port;
1813 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1820 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1823 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1833 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1835 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1840 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1909 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1917 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1920 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1921 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1922 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1925 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1932 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1933 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1935 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1946 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1979 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2062 u32 priority_mask, u8 port)
2068 nig_reg_rx_priority_mask_add = (port) ?
2073 nig_reg_rx_priority_mask_add = (port) ?
2078 nig_reg_rx_priority_mask_add = (port) ?
2083 if (port)
2088 if (port)
2093 if (port)
2109 port_mb[params->port].link_status), link_status);
2119 link_attr_sync[params->port]), link_attr);
2130 u8 port = params->port;
2140 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2153 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2165 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2171 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2173 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2175 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2177 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2180 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2183 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2186 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2190 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2194 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2203 nig_params->rx_cos_priority_mask[i], port);
2205 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2209 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2213 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2251 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2267 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2277 u8 port = params->port;
2278 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2341 u8 port = params->port;
2342 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2406 u8 port = params->port;
2412 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2417 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2420 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2427 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2428 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2429 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2435 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2436 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2437 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2438 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2439 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2440 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2446 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
2448 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2451 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2459 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2476 u8 port = params->port;
2480 /* Disable port */
2481 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2484 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2485 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2490 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2493 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2505 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2507 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2514 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2516 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2528 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2533 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2535 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2537 /* Enable port */
2538 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2547 * @port: port id
2550 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2558 u32 mdc_mdio_access, u8 port)
2577 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2580 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2825 offsetof(struct shmem2_region, eee_status[params->port]))
2891 port_feature_config[params->port].
2912 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2962 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
2979 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3005 eee_status[params->port]), eee_status);
3064 u8 port = params->port;
3076 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3227 u8 path, port;
3230 port = params->port;
3245 /* Figure out port swap value */
3253 port = port ^ 1;
3255 lane = (port<<1) + path;
3256 } else { /* Two port mode - no port swap */
3312 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3314 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3317 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3323 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3326 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3332 val = SERDES_RESET_BITS << (port*16);
3339 bnx2x_set_serdes_access(bp, port);
3341 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3353 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3354 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3363 u8 port;
3366 port = params->port;
3368 val = XGXS_RESET_BITS << (port*16);
3794 port_hw_config[params->port].default_cfg)) &
3985 port_hw_config[params->port].
4288 u32 shmem_base, u8 port,
4297 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4319 *gpio_port = port;
4332 params->shmem_base, params->port,
4374 port_hw_config[params->port].default_cfg)) &
4433 u8 port = params->port;
4437 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4458 port_hw_config[params->port].default_cfg)) &
4766 u8 port = params->port;
4773 port_mb[port].link_status));
4783 eee_status[params->port]));
4790 dev_info.port_hw_config[port].media_type);
4807 dev_info.port_hw_config[port].aeu_int_mask);
4821 link_attr_sync[params->port]);
4868 bnx2x_set_serdes_access(bp, params->port);
4888 params->port);
5311 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5312 params->port);
5322 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5323 params->port);
5818 u8 port = params->port;
5822 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5854 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5995 params->port);
6002 u8 port = params->port;
6033 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6036 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6038 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6040 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6041 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6042 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6044 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6045 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6048 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6059 NIG_REG_LATCH_STATUS_0 + port*8);
6065 + port*4,
6070 + port*4,
6076 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6086 u8 port = params->port;
6091 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6117 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6211 u8 port = params->port;
6222 port*0x18));
6224 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6245 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6266 u8 port = params->port;
6271 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6273 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6287 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6288 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6318 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6319 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6339 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6344 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6346 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6351 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6365 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6369 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6372 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6375 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6378 port*4, 1);
6390 + port*4, 1);
6392 port*4, 0);
6394 port*4, 1);
6562 params->port*4,
6575 (0x1ff << (params->port*16)));
6587 gpio_port = params->port;
6601 u8 port = params->port;
6603 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6615 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6619 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6625 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6629 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6631 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6649 u8 phy_idx, port = params->port;
6681 (params->port << 2), 1);
6684 (params->port << 2), 0xfc20);
6719 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6750 u8 port = params->port;
6775 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6776 port, (vars->phy_flags & PHY_XGXS_FLAG),
6777 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6780 port*0x18) > 0);
6782 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6784 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6787 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6788 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6792 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6910 bnx2x_rearm_latch_signal(bp, port,
6933 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
7001 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
7004 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7007 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7010 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
7013 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
7014 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
7022 u8 port)
7030 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
7089 u8 port)
7095 /* Boot port from external ROM */
7132 "bnx2x_8073_8727_external_rom_boot port %x:"
7134 port, fw_ver1);
7155 bnx2x_save_bcm_spirom_ver(bp, phy, port);
7158 "bnx2x_8073_8727_external_rom_boot port %x:"
7160 port, fw_ver1);
7326 gpio_port = params->port;
7363 port_hw_config[params->port].default_cfg)) &
7546 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7547 params->port);
7551 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7552 params->port);
7556 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7557 params->port);
7560 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7561 params->port);
7615 gpio_port = params->port;
7616 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7634 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7636 bnx2x_ext_phy_hw_reset(bp, params->port);
7649 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7720 gpio_port = params->port;
7731 u8 port = params->port;
7738 dev_info.port_hw_config[port].sfp_ctrl)) &
7740 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7741 "mode = %x\n", tx_en, port, tx_en_mode);
7870 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
8129 u8 gport = params->port;
8133 (params->port << 1);
8136 "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n",
8165 dev_info.port_hw_config[params->port].media_type);
8213 port_feature_config[params->port].config));
8269 params->port, vendor_name, vendor_pn);
8478 dev_info.port_hw_config[params->port].sfp_ctrl)) &
8492 "pin %x port %x mode %x\n",
8507 u8 port = params->port;
8511 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8633 port_feature_config[params->port].config));
8636 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8637 params->port);
8693 params->port, &gpio_num, &gpio_port) ==
8845 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8847 bnx2x_ext_phy_hw_reset(bp, params->port);
8919 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8927 dev_info.port_hw_config[params->port].sfp_ctrl))
8995 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
9108 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9168 u8 port;
9169 /* The PHY reset is controlled by GPIO 1. Fake the port number
9175 port = (swap_val && swap_override) ^ 1;
9177 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9300 dev_info.port_hw_config[params->port].sfp_ctrl))
9330 port_feature_config[params->port].
9414 u8 link_up = 0, oc_port = params->port;
9455 oc_port = BP_PATH(bp) + (params->port << 1);
9457 "8727 Power fault has been detected on port %d\n",
9516 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9517 params->port);
9521 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9522 params->port);
9525 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9526 params->port);
9587 u8 port)
9602 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9620 bnx2x_save_spirom_version(bp, port, 0,
9639 bnx2x_save_spirom_version(bp, port, 0,
9649 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9704 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9710 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9872 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9875 bnx2x_ext_phy_hw_reset(bp, params->port);
9952 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
10085 u8 port, initialize = 1;
10094 port = BP_PATH(bp);
10096 port = params->port;
10101 port);
10188 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10193 dev_info.port_hw_config[params->port].default_cfg)) &
10407 u8 port;
10411 port = BP_PATH(bp);
10413 port = params->port;
10418 port);
10435 u8 port;
10438 port = BP_PATH(bp);
10440 port = params->port;
10445 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10481 port);
10518 params->port*4) &
10526 params->port*4,
10538 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10586 params->port*4) &
10594 params->port*4,
10607 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10740 u8 port;
10748 * before determining the port.
10750 port = params->port;
10754 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10983 u8 port;
10990 * before determining the port.
10992 port = params->port;
10995 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11115 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11142 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11172 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11174 bnx2x_ext_phy_hw_reset(bp, params->port);
11197 bnx2x_save_spirom_version(bp, params->port,
11284 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11287 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11813 struct bnx2x_phy *phy, u8 port,
11826 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11830 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11834 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11838 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11850 u8 phy_index, u8 port)
11857 dev_info.port_hw_config[port].external_phy_config));
11862 dev_info.port_hw_config[port].external_phy_config2));
11871 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11878 dev_info.port_feature_config[port].link_config)) &
11896 port_hw_config[port].default_cfg)) &
11978 port * 0x10);
11984 port * 0x18);
11995 port);
12001 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
12002 port, phy->addr, phy->mdio_ctrl);
12004 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
12012 u8 port,
12018 phy_index, port);
12081 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
12091 port_mb[port].ext_phy_fw_version);
12104 ext_phy_fw_version2[port]);
12113 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12128 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12129 phy_type, port, phy_index);
12136 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12141 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12143 port, phy);
12157 port_feature_config[params->port].link_config2));
12161 port_hw_config[params->port].speed_capability_mask2));
12165 port_feature_config[params->port].link_config));
12169 port_hw_config[params->port].speed_capability_mask));
12277 params->shmem2_base, params->port,
12301 dev_info.port_hw_config[params->port].media_type);
12343 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12362 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12388 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12403 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12453 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12466 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12469 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12473 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12515 params->port));
12519 params->port));
12544 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12646 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12686 bnx2x_serdes_deassert(bp, params->port);
12703 u8 phy_index, port = params->port, clear_latch_ind = 0;
12704 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12711 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12718 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12722 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12723 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12727 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
12734 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12762 bnx2x_rearm_latch_signal(bp, port, 0);
12763 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12774 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12775 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12776 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12778 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12802 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12809 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
12830 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
12837 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12852 s8 port = 0;
12857 port ^= (swap_val && swap_override);
12858 bnx2x_ext_phy_hw_reset(bp, port);
12860 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12866 port_of_path = port;
12868 shmem_base = shmem_base_path[port];
12869 shmem2_base = shmem2_base_path[port];
12873 /* Extract the ext phy address for the port */
12875 port_of_path, &phy[port]) !=
12893 port);
12896 bnx2x_cl45_write(bp, &phy[port],
12914 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12916 port_of_path = port;
12921 phy_blk[port]->addr);
12922 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12927 bnx2x_cl45_read(bp, phy_blk[port],
12932 bnx2x_cl45_write(bp, phy_blk[port],
12944 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12947 bnx2x_cl45_read(bp, phy_blk[port],
12951 bnx2x_cl45_write(bp, phy_blk[port],
12957 bnx2x_cl45_read(bp, phy_blk[port],
12960 bnx2x_cl45_write(bp, phy_blk[port],
12966 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12976 s8 port;
12978 /* Use port1 because of the static port-swap */
12987 for (port = 0; port < PORT_MAX; port++) {
12995 shmem_base = shmem_base_path[port];
12996 shmem2_base = shmem2_base_path[port];
12998 /* Extract the ext phy address for the port */
13000 port, &phy) !=
13014 port);
13070 s8 port, reset_gpio;
13079 port = 1;
13081 /* Retrieve the reset gpio/port which control the reset.
13085 (u8 *)&reset_gpio, (u8 *)&port);
13087 /* Calculate the port based on port swap */
13088 port ^= (swap_val && swap_override);
13092 port);
13095 port);
13100 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13107 port_of_path = port;
13109 shmem_base = shmem_base_path[port];
13110 shmem2_base = shmem2_base_path[port];
13114 /* Extract the ext phy address for the port */
13116 port_of_path, &phy[port]) !=
13131 bnx2x_cl45_write(bp, &phy[port],
13145 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13147 port_of_path = port;
13151 phy_blk[port]->addr);
13152 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13156 bnx2x_cl45_write(bp, phy_blk[port],
13202 * it for single port alone
13260 /* Read the ext_phy_type for arbitrary port(0) */
13280 u8 port = params->port;
13285 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13302 params->port);
13351 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13364 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13399 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13410 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13424 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13428 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13451 u8 led_change, port = params->port;
13455 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13597 port_hw_config[params->port].default_cfg))
13617 u8 port)
13624 port, &phy)
13640 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13659 u8 port)
13667 port,
13676 shmem2_base, port, &phy)
13683 gpio_port = port;
13704 dev_info.port_hw_config[port].aeu_int_mask);
13710 if (port == 0)