Lines Matching defs:cmac
97 static int pmread(struct cmac *cmac, u32 reg, u32 * data32)
99 t1_tpi_read(cmac->adapter, OFFSET(reg), data32);
103 static int pmwrite(struct cmac *cmac, u32 reg, u32 data32)
105 t1_tpi_write(cmac->adapter, OFFSET(reg), data32);
110 static int pm3393_reset(struct cmac *cmac)
123 static int pm3393_interrupt_enable(struct cmac *cmac)
129 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff);
130 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff);
131 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff);
132 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff);
135 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
136 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
137 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
138 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
140 pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0xffff);
141 pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0xffff);
142 pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0xffff);
143 pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0xffff);
144 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0xffff);
145 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0xffff);
146 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0xffff);
147 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0xffff);
148 pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0xffff);
153 pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE,
157 pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE);
159 writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE);
163 static int pm3393_interrupt_disable(struct cmac *cmac)
168 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0);
169 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0);
170 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0);
171 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0);
172 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
173 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
174 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
175 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
176 pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0);
177 pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0);
178 pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0);
179 pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0);
180 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0);
181 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0);
182 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0);
183 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0);
184 pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0);
187 pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0);
190 t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer);
192 t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer);
202 static int pm3393_interrupt_clear(struct cmac *cmac)
211 pmread(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS, &val32);
212 pmread(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS, &val32);
213 pmread(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS, &val32);
214 pmread(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS, &val32);
215 pmread(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT, &val32);
216 pmread(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS, &val32);
217 pmread(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT, &val32);
218 pmread(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS, &val32);
219 pmread(cmac, SUNI1x10GEXP_REG_RXXG_INTERRUPT, &val32);
220 pmread(cmac, SUNI1x10GEXP_REG_TXXG_INTERRUPT, &val32);
221 pmread(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT, &val32);
222 pmread(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION,
224 pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS, &val32);
225 pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE, &val32);
229 pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, &val32);
233 t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer);
235 t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer);
239 pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE);
241 writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE);
247 static int pm3393_interrupt_handler(struct cmac *cmac)
252 pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS,
254 if (netif_msg_intr(cmac->adapter))
255 dev_dbg(&cmac->adapter->pdev->dev, "PM3393 intr cause 0x%x\n",
259 pm3393_interrupt_clear(cmac);
264 static int pm3393_enable(struct cmac *cmac, int which)
267 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1,
273 if (cmac->instance->fc & PAUSE_RX)
275 if (cmac->instance->fc & PAUSE_TX)
277 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, val);
280 cmac->instance->enabled |= which;
284 static int pm3393_enable_port(struct cmac *cmac, int which)
287 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_CONTROL,
290 memset(&cmac->stats, 0, sizeof(struct cmac_statistics));
292 pm3393_enable(cmac, which);
299 t1_link_changed(cmac->adapter, 0);
303 static int pm3393_disable(struct cmac *cmac, int which)
306 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, RXXG_CONF1_VAL);
308 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, TXXG_CONF1_VAL);
316 cmac->instance->enabled &= ~which;
320 static int pm3393_loopback_enable(struct cmac *cmac)
325 static int pm3393_loopback_disable(struct cmac *cmac)
330 static int pm3393_set_mtu(struct cmac *cmac, int mtu)
332 int enabled = cmac->instance->enabled;
341 pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
343 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH, mtu);
344 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE, mtu);
347 pm3393_enable(cmac, enabled);
351 static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm)
353 int enabled = cmac->instance->enabled & MAC_DIRECTION_RX;
358 pm3393_disable(cmac, MAC_DIRECTION_RX);
360 pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, &rx_mode);
363 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2,
372 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, 0xffff);
373 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, 0xffff);
374 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, 0xffff);
375 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, 0xffff);
388 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]);
389 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, mc_filter[1]);
390 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, mc_filter[2]);
391 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, mc_filter[3]);
395 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode);
398 pm3393_enable(cmac, MAC_DIRECTION_RX);
403 static int pm3393_get_speed_duplex_fc(struct cmac *cmac, int *speed,
411 *fc = cmac->instance->fc;
415 static int pm3393_set_speed_duplex_fc(struct cmac *cmac, int speed, int duplex,
425 if (fc != cmac->instance->fc) {
426 cmac->instance->fc = (u8) fc;
427 if (cmac->instance->enabled & MAC_DIRECTION_TX)
428 pm3393_enable(cmac, MAC_DIRECTION_TX);
448 static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,
499 static int pm3393_macaddress_get(struct cmac *cmac, u8 mac_addr[6])
501 memcpy(mac_addr, cmac->instance->mac_addr, ETH_ALEN);
505 static int pm3393_macaddress_set(struct cmac *cmac, u8 ma[6])
507 u32 val, lo, mid, hi, enabled = cmac->instance->enabled;
528 memcpy(cmac->instance->mac_addr, ma, ETH_ALEN);
536 pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
539 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_15_0, lo);
540 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_31_16, mid);
541 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_47_32, hi);
544 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_15_0, lo);
545 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_31_16, mid);
546 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_47_32, hi);
552 pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, &val);
554 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
556 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW, lo);
557 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID, mid);
558 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH, hi);
561 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
564 pm3393_enable(cmac, enabled);
568 static void pm3393_destroy(struct cmac *cmac)
570 kfree(cmac);
593 static struct cmac *pm3393_mac_create(adapter_t *adapter, int index)
595 struct cmac *cmac;
597 cmac = kzalloc(sizeof(*cmac) + sizeof(cmac_instance), GFP_KERNEL);
598 if (!cmac)
601 cmac->ops = &pm3393_ops;
602 cmac->instance = (cmac_instance *) (cmac + 1);
603 cmac->adapter = adapter;
604 cmac->instance->fc = PAUSE_TX | PAUSE_RX;
687 return cmac;