Cross Reference: /drivers/net/ethernet/chelsio/cxgb3/t3

Lines Matching refs:mc7
137  *	@mc7: identifies MC7 to read from
145 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
151 	unsigned int size64 = mc7->size / 8;	/* # of 64-bit words */
152 	struct adapter *adap = mc7->adapter;
157 	start *= (8 << mc7->width);
162 		for (i = (1 << mc7->width) - 1; i >= 0; --i) {
166 			t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, start);
167 			t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0);
168 			val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP);
171 						  mc7->offset + A_MC7_BD_OP);
175 			val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1);
176 			if (mc7->width == 0) {
178 						    mc7->offset +
182 				if (mc7->width > 1)
183 					val >>= shift[mc7->width];
184 				val64 |= (u64) val << (step[mc7->width] * i);
1757 static void mc7_intr_handler(struct mc7 *mc7)
1759 	struct adapter *adapter = mc7->adapter;
1760 	u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE);
1763 		mc7->stats.corr_err++;
1765 			"data 0x%x 0x%x 0x%x\n", mc7->name,
1766 			t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR),
1767 			t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0),
1768 			t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1),
1769 			t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2));
1773 		mc7->stats.uncorr_err++;
1775 			 "data 0x%x 0x%x 0x%x\n", mc7->name,
1776 			 t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR),
1777 			 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0),
1778 			 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1),
1779 			 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2));
1783 		mc7->stats.parity_err++;
1785 			 mc7->name, G_PE(cause));
1793 					   mc7->offset + A_MC7_ERR_ADDR);
1794 		mc7->stats.addr_err++;
1796 			 mc7->name, addr);
1802 	t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause);
3160 static int mc7_init(struct mc7 *mc7, unsigned int mc7_clock, int mem_type)
3175 	struct adapter *adapter = mc7->adapter;
3178 	if (!mc7->size)
3181 	val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
3186 	t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN);
3187 	val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);	/* flush */
3191 		t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN);
3192 		t3_read_reg(adapter, mc7->offset + A_MC7_CAL);
3194 		if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) &
3197 			       mc7->name);
3202 	t3_write_reg(adapter, mc7->offset + A_MC7_PARM,
3208 	t3_write_reg(adapter, mc7->offset + A_MC7_CFG,
3210 	t3_read_reg(adapter, mc7->offset + A_MC7_CFG);	/* flush */
3213 		t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB,
3218 	if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||
3219 	    wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE2, 0) ||
3220 	    wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE3, 0) ||
3221 	    wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))
3225 		t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100);
3226 		t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLRST, 0);
3230 	if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||
3231 	    wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||
3232 	    wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||
3233 	    wrreg_wait(adapter, mc7->offset + A_MC7_MODE,
3235 	    wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val | 0x380) ||
3236 	    wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))
3243 	t3_write_reg(adapter, mc7->offset + A_MC7_REF,
3245 	t3_read_reg(adapter, mc7->offset + A_MC7_REF);	/* flush */
3247 	t3_write_reg(adapter, mc7->offset + A_MC7_ECC, F_ECCGENEN | F_ECCCHKEN);
3248 	t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0);
3249 	t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0);
3250 	t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END,
3251 		     (mc7->size << width) - 1);
3252 	t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1));
3253 	t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP);	/* flush */
3258 		val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP);
3261 		CH_ERR(adapter, "%s MC7 BIST timed out\n", mc7->name);
3266 	t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY);
3492 static void mc7_prep(struct adapter *adapter, struct mc7 *mc7,
3497 	mc7->adapter = adapter;
3498 	mc7->name = name;
3499 	mc7->offset = base_addr - MC7_PMRX_BASE_ADDR;
3500 	cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
3501 	mc7->size = G_DEN(cfg) == M_DEN ? 0 : mc7_calc_size(cfg);
3502 	mc7->width = G_WIDTH(cfg);