Lines Matching refs:lp
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
343 Fix initialisation problem with lp->timeout in
404 lp->rst not run because lp->ibn not initialised -
420 Change dev->interrupt to lp->interrupt to ensure
682 imr |= lp->irq_en;\
688 imr &= ~lp->irq_en;\
693 imr |= lp->irq_mask;\
699 imr &= ~lp->irq_mask;\
888 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
892 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
954 static int PCI_signature(char *name, struct de4x5_private *lp);
957 static int de4x5_bad_srom(struct de4x5_private *lp);
985 static int an_exception(struct de4x5_private *lp);
1099 struct de4x5_private *lp = netdev_priv(dev);
1106 if (lp->bus == EISA) {
1123 lp->useSROM = false;
1124 if (lp->bus == PCI) {
1125 PCI_signature(name, lp);
1144 skb_queue_head_init(&lp->cache.queue);
1145 lp->cache.gepc = GEP_INIT;
1146 lp->asBit = GEP_SLNK;
1147 lp->asPolarity = GEP_SLNK;
1148 lp->asBitValid = ~0;
1149 lp->timeout = -1;
1150 lp->gendev = gendev;
1151 spin_lock_init(&lp->lock);
1152 init_timer(&lp->timer);
1153 lp->timer.function = (void (*)(unsigned long))de4x5_ast;
1154 lp->timer.data = (unsigned long)dev;
1160 lp->autosense = lp->params.autosense;
1161 if (lp->chipset != DC21140) {
1162 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1163 lp->params.autosense = TP;
1165 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1166 lp->params.autosense = BNC;
1169 lp->fdx = lp->params.fdx;
1170 sprintf(lp->adapter_name,"%s (%s)", name, dev_name(gendev));
1172 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1174 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1176 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1177 &lp->dma_rings, GFP_ATOMIC);
1178 if (lp->rx_ring == NULL) {
1182 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1190 lp->rx_ring[i].status = 0;
1191 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1192 lp->rx_ring[i].buf = 0;
1193 lp->rx_ring[i].next = 0;
1194 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1201 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1204 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1207 lp->rx_ring[i].status = 0;
1208 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1209 lp->rx_ring[i].buf =
1211 lp->rx_ring[i].next = 0;
1212 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1220 lp->rxRingSize = NUM_RX_DESC;
1221 lp->txRingSize = NUM_TX_DESC;
1224 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1225 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1228 outl(lp->dma_rings, DE4X5_RRBA);
1229 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1233 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1234 lp->irq_en = IMR_NIM | IMR_AIM;
1237 create_packet(dev, lp->frame, sizeof(lp->frame));
1240 i = lp->cfrv & 0x000000fe;
1241 if ((lp->chipset == DC21140) && (i == 0x20)) {
1242 lp->rx_ovf = 1;
1246 if (lp->useSROM) {
1247 lp->state = INITIALISED;
1249 dma_free_coherent (gendev, lp->dma_size,
1250 lp->rx_ring, lp->dma_rings);
1256 lp->state = CLOSED;
1261 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1266 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1280 dma_free_coherent (gendev, lp->dma_size,
1281 lp->rx_ring, lp->dma_rings);
1295 struct de4x5_private *lp = netdev_priv(dev);
1301 for (i=0; i<lp->rxRingSize; i++) {
1317 spin_lock_init(&lp->lock);
1318 lp->state = OPEN;
1322 lp->adapter_name, dev)) {
1325 lp->adapter_name, dev)) {
1331 lp->state = CLOSED;
1339 lp->interrupt = UNMASK_INTERRUPTS;
1385 struct de4x5_private *lp = netdev_priv(dev);
1391 if (!lp->useSROM) {
1392 if (lp->phy[lp->active].id != 0) {
1393 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1395 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1405 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1406 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1410 if (lp->chipset == DC21140) {
1413 lp->setup_f = PERFECT;
1414 outl(lp->dma_rings, DE4X5_RRBA);
1415 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1418 lp->rx_new = lp->rx_old = 0;
1419 lp->tx_new = lp->tx_old = 0;
1421 for (i = 0; i < lp->rxRingSize; i++) {
1422 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1425 for (i = 0; i < lp->txRingSize; i++) {
1426 lp->tx_ring[i].status = cpu_to_le32(0);
1434 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1441 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1451 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1452 lp->tx_old = lp->tx_new;
1463 struct de4x5_private *lp = netdev_priv(dev);
1468 if (!lp->tx_enable) /* Cannot send for now */
1476 spin_lock_irqsave(&lp->lock, flags);
1478 spin_unlock_irqrestore(&lp->lock, flags);
1481 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1485 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1486 if (lp->interrupt) {
1492 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1496 if (!skb_queue_empty(&lp->cache.queue) && !lp->interrupt) {
1502 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1503 spin_lock_irqsave(&lp->lock, flags);
1506 lp->stats.tx_bytes += skb->len;
1509 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1515 spin_unlock_irqrestore(&lp->lock, flags);
1520 lp->cache.lock = 0;
1540 struct de4x5_private *lp;
1545 lp = netdev_priv(dev);
1546 spin_lock(&lp->lock);
1551 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1560 if (!(sts & lp->irq_mask)) break;/* All done */
1570 lp->irq_mask &= ~IMR_LFM;
1581 spin_unlock(&lp->lock);
1587 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1588 while (!skb_queue_empty(&lp->cache.queue) && !netif_queue_stopped(dev) && lp->tx_enable) {
1591 lp->cache.lock = 0;
1594 lp->interrupt = UNMASK_INTERRUPTS;
1596 spin_unlock(&lp->lock);
1604 struct de4x5_private *lp = netdev_priv(dev);
1609 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1610 entry=lp->rx_new) {
1611 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1613 if (lp->rx_ovf) {
1621 lp->rx_old = entry;
1625 if (lp->tx_enable) lp->linkOK++;
1627 lp->stats.rx_errors++; /* Update the error stats. */
1628 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1629 if (status & RD_CE) lp->stats.rx_crc_errors++;
1630 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1631 if (status & RD_TL) lp->stats.rx_length_errors++;
1632 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1633 if (status & RD_CS) lp->pktStats.rx_collision++;
1634 if (status & RD_DB) lp->pktStats.rx_dribble++;
1635 if (status & RD_OF) lp->pktStats.rx_overflow++;
1638 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1644 lp->stats.rx_dropped++;
1654 lp->stats.rx_packets++;
1655 lp->stats.rx_bytes += pkt_len;
1660 for (;lp->rx_old!=entry;lp->rx_old=(lp->rx_old + 1)%lp->rxRingSize) {
1661 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1664 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1671 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1678 de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1680 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1681 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1683 if ((u_long) lp->tx_skb[entry] > 1)
1684 dev_kfree_skb_irq(lp->tx_skb[entry]);
1685 lp->tx_skb[entry] = NULL;
1694 struct de4x5_private *lp = netdev_priv(dev);
1699 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1700 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1705 lp->stats.tx_errors++;
1706 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1707 if (status & TD_LC) lp->stats.tx_window_errors++;
1708 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1709 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1710 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1716 lp->stats.tx_packets++;
1717 if (lp->tx_enable) lp->linkOK++;
1720 lp->stats.collisions += ((status & TD_EC) ? 16 :
1724 if (lp->tx_skb[entry] != NULL)
1725 de4x5_free_tx_buff(lp, entry);
1729 lp->tx_old = (lp->tx_old + 1) % lp->txRingSize;
1734 if (lp->interrupt)
1746 struct de4x5_private *lp = netdev_priv(dev);
1750 if (lp->useSROM)
1752 else if (lp->chipset == DC21140)
1754 else if (lp->chipset == DC21041)
1756 else if (lp->chipset == DC21040)
1758 lp->linkOK = 0;
1765 mod_timer(&lp->timer, jiffies + dt);
1771 struct de4x5_private *lp = netdev_priv(dev);
1776 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1794 struct de4x5_private *lp = netdev_priv(dev);
1802 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1803 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1804 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1815 struct de4x5_private *lp = netdev_priv(dev);
1836 lp->state = CLOSED;
1851 struct de4x5_private *lp = netdev_priv(dev);
1854 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1856 return &lp->stats;
1862 struct de4x5_private *lp = netdev_priv(dev);
1867 lp->pktStats.bins[i]++;
1873 lp->pktStats.broadcast++;
1875 lp->pktStats.multicast++;
1878 lp->pktStats.unicast++;
1881 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1882 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1883 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1898 struct de4x5_private *lp = netdev_priv(dev);
1899 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1900 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1902 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1903 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1904 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1905 lp->tx_skb[lp->tx_new] = skb;
1906 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1909 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1919 struct de4x5_private *lp = netdev_priv(dev);
1923 if (lp->state == OPEN) {
1931 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1934 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1949 struct de4x5_private *lp = netdev_priv(dev);
1964 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
1976 lp->setup_frame[byte] |= bit;
2003 struct de4x5_private *lp;
2021 lp = netdev_priv(dev);
2024 lp->cfrv = (u_short) inl(PCI_CFRV);
2053 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2055 lp->chipset = device;
2056 lp->bus = EISA;
2129 struct de4x5_private *lp = netdev_priv(dev);
2141 lp->device = PCI_SLOT(this_dev->devfn);
2142 lp->bus_num = pb;
2149 lp->chipset = device;
2165 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2172 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2204 struct de4x5_private *lp;
2230 lp = netdev_priv(dev);
2231 lp->bus = PCI;
2232 lp->bus_num = 0;
2235 if (lp->bus_num != pb) {
2236 lp->bus_num = pb;
2241 lp->cfrv = pdev->revision;
2244 lp->device = dev_num;
2245 lp->bus_num = pb;
2249 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2251 lp->chipset = device;
2362 struct de4x5_private *lp = netdev_priv(dev);
2367 lp->c_media = AUTO; /* Bogus last media */
2369 lp->media = INIT;
2370 lp->tcount = 0;
2374 return lp->media;
2392 struct de4x5_private *lp = netdev_priv(dev);
2397 switch (lp->media) {
2400 lp->tx_enable = false;
2401 lp->timeout = -1;
2403 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2404 lp->media = TP;
2405 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2406 lp->media = BNC_AUI;
2407 } else if (lp->autosense == EXT_SIA) {
2408 lp->media = EXT_SIA;
2410 lp->media = NC;
2412 lp->local_state = 0;
2448 if (lp->media != lp->c_media) {
2450 lp->c_media = lp->media;
2452 lp->media = INIT;
2453 lp->tx_enable = false;
2465 struct de4x5_private *lp = netdev_priv(dev);
2469 switch (lp->local_state) {
2472 lp->local_state++;
2477 if (!lp->tx_enable) {
2482 if (linkBad && (lp->autosense == AUTO)) {
2483 lp->local_state = 0;
2484 lp->media = next_state;
2489 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2490 lp->media = suspect_state;
2504 struct de4x5_private *lp = netdev_priv(dev);
2508 switch (lp->local_state) {
2510 if (lp->linkOK) {
2511 lp->media = prev_state;
2513 lp->local_state++;
2523 lp->local_state--;
2524 lp->media = prev_state;
2526 lp->media = INIT;
2527 lp->tcount++;
2546 struct de4x5_private *lp = netdev_priv(dev);
2551 switch (lp->media) {
2554 lp->tx_enable = false;
2555 lp->timeout = -1;
2557 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2558 lp->media = TP; /* On chip auto negotiation is broken */
2559 } else if (lp->autosense == TP) {
2560 lp->media = TP;
2561 } else if (lp->autosense == BNC) {
2562 lp->media = BNC;
2563 } else if (lp->autosense == AUI) {
2564 lp->media = AUI;
2566 lp->media = NC;
2568 lp->local_state = 0;
2573 if (lp->timeout < 0) {
2584 lp->media = ANS;
2586 lp->media = AUI;
2593 if (!lp->tx_enable) {
2600 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2601 lp->media = TP;
2604 lp->local_state = 1;
2608 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2609 lp->media = ANS_SUSPECT;
2619 if (!lp->tx_enable) {
2620 if (lp->timeout < 0) {
2630 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2632 lp->media = AUI; /* Non selected port activity */
2634 lp->media = BNC;
2638 lp->local_state = 1;
2642 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2643 lp->media = TP_SUSPECT;
2653 if (!lp->tx_enable) {
2654 if (lp->timeout < 0) {
2664 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2665 lp->media = BNC;
2668 lp->local_state = 1;
2672 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2673 lp->media = AUI_SUSPECT;
2683 switch (lp->local_state) {
2685 if (lp->timeout < 0) {
2695 lp->local_state++; /* Ensure media connected */
2701 if (!lp->tx_enable) {
2706 lp->local_state = 0;
2707 lp->media = NC;
2712 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2713 lp->media = BNC_SUSPECT;
2728 if (lp->media != lp->c_media) {
2730 lp->c_media = lp->media;
2732 lp->media = INIT;
2733 lp->tx_enable = false;
2748 struct de4x5_private *lp = netdev_priv(dev);
2753 switch(lp->media) {
2755 if (lp->timeout < 0) {
2757 lp->tx_enable = false;
2758 lp->linkOK = 0;
2764 if (lp->useSROM) {
2766 lp->tcount++;
2769 srom_exec(dev, lp->phy[lp->active].gep);
2770 if (lp->infoblock_media == ANS) {
2771 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2772 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2775 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2777 if (lp->autosense == _100Mb) {
2778 lp->media = _100Mb;
2779 } else if (lp->autosense == _10Mb) {
2780 lp->media = _10Mb;
2781 } else if ((lp->autosense == AUTO) &&
2784 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2785 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2786 lp->media = ANS;
2787 } else if (lp->autosense == AUTO) {
2788 lp->media = SPD_DET;
2790 lp->media = _100Mb;
2792 lp->media = NC;
2795 lp->local_state = 0;
2801 switch (lp->local_state) {
2803 if (lp->timeout < 0) {
2804 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2811 lp->local_state = 0;
2812 lp->media = SPD_DET;
2814 lp->local_state++;
2824 lp->media = SPD_DET;
2825 lp->local_state = 0;
2827 lp->tmp = MII_SR_ASSC;
2828 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2829 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2833 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
2834 lp->media = _100Mb;
2836 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
2838 lp->media = _10Mb;
2849 if (lp->timeout < 0) {
2850 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2858 lp->media = _100Mb;
2859 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2860 lp->media = _10Mb;
2862 lp->media = NC;
2870 if (!lp->tx_enable) {
2874 if (!lp->linkOK && (lp->autosense == AUTO)) {
2875 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2876 lp->media = INIT;
2877 lp->tcount++;
2888 if (!lp->tx_enable) {
2892 if (!lp->linkOK && (lp->autosense == AUTO)) {
2893 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2894 lp->media = INIT;
2895 lp->tcount++;
2903 if (lp->media != lp->c_media) {
2905 lp->c_media = lp->media;
2907 lp->media = INIT;
2908 lp->tx_enable = false;
2932 struct de4x5_private *lp = netdev_priv(dev);
2937 switch (lp->media) {
2939 if (lp->timeout < 0) {
2941 lp->tx_enable = false;
2942 lp->linkOK = 0;
2943 lp->timeout = -1;
2945 if (lp->params.autosense & ~AUTO) {
2947 if (lp->media != lp->params.autosense) {
2948 lp->tcount++;
2949 lp->media = INIT;
2952 lp->media = INIT;
2958 if (lp->autosense == _100Mb) {
2959 lp->media = _100Mb;
2960 } else if (lp->autosense == _10Mb) {
2961 lp->media = _10Mb;
2962 } else if (lp->autosense == TP) {
2963 lp->media = TP;
2964 } else if (lp->autosense == BNC) {
2965 lp->media = BNC;
2966 } else if (lp->autosense == AUI) {
2967 lp->media = AUI;
2969 lp->media = SPD_DET;
2970 if ((lp->infoblock_media == ANS) &&
2973 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2974 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2975 lp->media = ANS;
2978 lp->local_state = 0;
2984 switch (lp->local_state) {
2986 if (lp->timeout < 0) {
2987 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2994 lp->local_state = 0;
2995 lp->media = SPD_DET;
2997 lp->local_state++;
3008 lp->media = SPD_DET;
3009 lp->local_state = 0;
3011 lp->tmp = MII_SR_ASSC;
3012 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3013 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3017 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
3018 lp->media = _100Mb;
3020 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
3021 lp->media = _10Mb;
3032 if (!lp->tx_enable) {
3033 if (lp->timeout < 0) {
3043 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3044 lp->media = BNC;
3047 lp->local_state = 1;
3051 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3052 lp->media = AUI_SUSPECT;
3062 switch (lp->local_state) {
3064 if (lp->timeout < 0) {
3074 lp->local_state++; /* Ensure media connected */
3080 if (!lp->tx_enable) {
3085 lp->local_state = 0;
3086 lp->tcount++;
3087 lp->media = INIT;
3092 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3093 lp->media = BNC_SUSPECT;
3106 lp->tcount++;
3107 lp->media = INIT;
3110 if (lp->media == _100Mb) {
3112 lp->media = SPD_DET;
3117 lp->media = SPD_DET;
3121 if (lp->media == ANS) { /* Do MII parallel detection */
3123 lp->media = _100Mb;
3125 lp->media = _10Mb;
3128 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3129 (((lp->media == _10Mb) || (lp->media == TP) ||
3130 (lp->media == BNC) || (lp->media == AUI)) &&
3134 lp->tcount++;
3135 lp->media = INIT;
3141 if (!lp->tx_enable) {
3145 if (!lp->linkOK && (lp->autosense == AUTO)) {
3146 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3147 lp->media = INIT;
3148 lp->tcount++;
3157 if (!lp->tx_enable) {
3161 if (!lp->linkOK && (lp->autosense == AUTO)) {
3162 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3163 lp->media = INIT;
3164 lp->tcount++;
3172 lp->tcount++;
3173 printk("Huh?: media:%02x\n", lp->media);
3174 lp->media = INIT;
3184 struct de4x5_private *lp = netdev_priv(dev);
3186 return lp->infoleaf_fn(dev);
3197 struct de4x5_private *lp = netdev_priv(dev);
3199 lp->fdx = false;
3200 if (lp->infoblock_media == lp->media)
3203 switch(lp->infoblock_media) {
3205 if (!lp->params.fdx) return -1;
3206 lp->fdx = true;
3208 if (lp->params.fdx && !lp->fdx) return -1;
3209 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3210 lp->media = _10Mb;
3212 lp->media = TP;
3217 lp->media = BNC;
3221 lp->media = AUI;
3225 if (!lp->params.fdx) return -1;
3226 lp->fdx = true;
3228 if (lp->params.fdx && !lp->fdx) return -1;
3229 lp->media = _100Mb;
3233 lp->media = _100Mb;
3237 if (!lp->params.fdx) return -1;
3238 lp->fdx = true;
3240 if (lp->params.fdx && !lp->fdx) return -1;
3241 lp->media = _100Mb;
3245 lp->media = ANS;
3246 lp->fdx = lp->params.fdx;
3251 lp->infoblock_media);
3261 struct de4x5_private *lp = netdev_priv(dev);
3265 if (lp->media != lp->c_media) {
3267 lp->c_media = lp->media; /* Stop scrolling media messages */
3270 spin_lock_irqsave(&lp->lock, flags);
3273 lp->tx_enable = true;
3274 spin_unlock_irqrestore(&lp->lock, flags);
3288 struct de4x5_private *lp = netdev_priv(dev);
3292 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3293 if (lp->timeout < 0) {
3294 if (lp->useSROM) {
3295 if (lp->phy[lp->active].rst) {
3296 srom_exec(dev, lp->phy[lp->active].rst);
3297 srom_exec(dev, lp->phy[lp->active].rst);
3298 } else if (lp->rst) { /* Type 5 infoblock reset */
3299 srom_exec(dev, lp->rst);
3300 srom_exec(dev, lp->rst);
3305 if (lp->useMII) {
3306 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3309 if (lp->useMII) {
3312 } else if (lp->chipset == DC21140) {
3322 struct de4x5_private *lp = netdev_priv(dev);
3326 if (lp->timeout < 0) {
3327 lp->timeout = msec/100;
3328 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3340 if ((lp->chipset == DC21041) || lp->useSROM) {
3348 if (!(sts & irqs) && --lp->timeout) {
3351 lp->timeout = -1;
3360 struct de4x5_private *lp = netdev_priv(dev);
3364 if (lp->timeout < 0) {
3365 lp->timeout = msec/100;
3370 if (sisr && --lp->timeout) {
3373 lp->timeout = -1;
3389 struct de4x5_private *lp = netdev_priv(dev);
3390 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3392 if (lp->timeout < 0) {
3395 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3399 lp->timeout = msec/SAMPLE_INTERVAL;
3403 if (lp->phy[lp->active].id || lp->useSROM) {
3408 if (!(gep & ret) && --lp->timeout) {
3411 lp->timeout = -1;
3420 struct de4x5_private *lp = netdev_priv(dev);
3422 if (lp->timeout < 0) {
3423 lp->timeout = 1;
3426 if (lp->timeout--) {
3429 lp->timeout = -1;
3442 struct de4x5_private *lp = netdev_priv(dev);
3446 if (lp->timeout < 0) {
3447 lp->timeout = msec/100;
3450 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3453 if (test && --lp->timeout) {
3456 lp->timeout = -1;
3465 struct de4x5_private *lp = netdev_priv(dev);
3469 if (lp->useMII) {
3470 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3471 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3472 spd &= lp->phy[lp->active].spd.mask;
3473 } else if (!lp->useSROM) { /* de500-xa */
3476 if ((lp->ibn == 2) || !lp->asBitValid)
3477 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3479 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3480 (lp->linkOK & ~lp->asBitValid);
3489 struct de4x5_private *lp = netdev_priv(dev);
3492 if (lp->useMII) {
3494 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3495 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3496 } else if (!lp->useSROM) { /* de500-xa */
3499 if ((lp->ibn == 2) || !lp->asBitValid)
3500 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3502 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3503 (lp->linkOK & ~lp->asBitValid);
3510 struct de4x5_private *lp = netdev_priv(dev);
3513 if (lp->useMII) {
3515 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3516 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3517 } else if (!lp->useSROM) { /* de500-xa */
3520 if ((lp->ibn == 2) || !lp->asBitValid)
3521 return ((lp->chipset & ~0x00ff) == DC2114x) ?
3525 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3526 (lp->linkOK & ~lp->asBitValid);
3533 struct de4x5_private *lp = netdev_priv(dev);
3536 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3537 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3538 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3552 struct de4x5_private *lp = netdev_priv(dev);
3556 if (lp->timeout < 0) {
3557 lp->timeout = msec/100;
3559 lp->tmp = lp->tx_new; /* Remember the ring position */
3560 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3561 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
3568 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3569 (--lp->timeout)) {
3573 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3574 lp->timeout) {
3579 lp->timeout = -1;
3593 struct de4x5_private *lp = netdev_priv(dev);
3606 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3608 ret = lp->rx_skb[index];
3609 lp->rx_skb[index] = p;
3618 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3624 if (index < lp->rx_old) { /* Wrapped buffer */
3625 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3626 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3627 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3629 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3639 struct de4x5_private *lp = netdev_priv(dev);
3642 for (i=0; i<lp->rxRingSize; i++) {
3643 if ((u_long) lp->rx_skb[i] > 1) {
3644 dev_kfree_skb(lp->rx_skb[i]);
3646 lp->rx_ring[i].status = 0;
3647 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3654 struct de4x5_private *lp = netdev_priv(dev);
3657 for (i=0; i<lp->txRingSize; i++) {
3658 if (lp->tx_skb[i])
3659 de4x5_free_tx_buff(lp, i);
3660 lp->tx_ring[i].status = 0;
3664 __skb_queue_purge(&lp->cache.queue);
3677 struct de4x5_private *lp = netdev_priv(dev);
3681 if (!lp->cache.save_cnt) {
3688 lp->cache.save_cnt++;
3696 struct de4x5_private *lp = netdev_priv(dev);
3701 if (lp->cache.save_cnt) {
3703 outl(lp->dma_rings, DE4X5_RRBA);
3704 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3707 lp->rx_new = lp->rx_old = 0;
3708 lp->tx_new = lp->tx_old = 0;
3710 for (i = 0; i < lp->rxRingSize; i++) {
3711 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3714 for (i = 0; i < lp->txRingSize; i++) {
3715 lp->tx_ring[i].status = cpu_to_le32(0);
3719 lp->cache.save_cnt--;
3727 struct de4x5_private *lp = netdev_priv(dev);
3732 lp->cache.csr0 = inl(DE4X5_BMR);
3733 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3734 lp->cache.csr7 = inl(DE4X5_IMR);
3738 outl(lp->cache.csr0, DE4X5_BMR);
3739 outl(lp->cache.csr6, DE4X5_OMR);
3740 outl(lp->cache.csr7, DE4X5_IMR);
3741 if (lp->chipset == DC21140) {
3742 gep_wr(lp->cache.gepc, dev);
3743 gep_wr(lp->cache.gep, dev);
3745 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3746 lp->cache.csr15);
3755 struct de4x5_private *lp = netdev_priv(dev);
3757 __skb_queue_tail(&lp->cache.queue, skb);
3763 struct de4x5_private *lp = netdev_priv(dev);
3765 __skb_queue_head(&lp->cache.queue, skb);
3771 struct de4x5_private *lp = netdev_priv(dev);
3773 return __skb_dequeue(&lp->cache.queue);
3783 struct de4x5_private *lp = netdev_priv(dev);
3787 if (lp->timeout < 0) {
3788 lp->timeout = msec/100;
3799 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3802 lp->timeout = -1;
3811 struct de4x5_private *lp = netdev_priv(dev);
3830 struct de4x5_private *lp = netdev_priv(dev);
3834 if (lp->useSROM) {
3835 if (lp->ibn == 3) {
3836 srom_exec(dev, lp->phy[lp->active].rst);
3837 srom_exec(dev, lp->phy[lp->active].gep);
3841 csr15 = lp->cache.csr15;
3842 csr14 = lp->cache.csr14;
3843 csr13 = lp->cache.csr13;
3844 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3845 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3901 PCI_signature(char *name, struct de4x5_private *lp)
3905 if (lp->chipset == DC21040) {
3909 int tmp = *((char *)&lp->srom + 19) * 3;
3910 strncpy(name, (char *)&lp->srom + 26 + tmp, 8);
3920 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3921 ((lp->chipset == DC21041) ? "DC21041" :
3922 ((lp->chipset == DC21140) ? "DC21140" :
3923 ((lp->chipset == DC21142) ? "DC21142" :
3924 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3927 if (lp->chipset != DC21041) {
3928 lp->useSROM = true; /* card is not recognisably DEC */
3930 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3931 lp->useSROM = true;
3949 struct de4x5_private *lp = netdev_priv(dev);
3951 if (lp->chipset == DC21040) {
3952 if (lp->bus == EISA) {
3959 __le16 *p = (__le16 *)((char *)&lp->srom + SROM_HWADD);
3970 p = (__le16 *)&lp->srom;
3975 de4x5_dbg_srom(&lp->srom);
4028 struct de4x5_private *lp = netdev_priv(dev);
4030 broken = de4x5_bad_srom(lp);
4036 if (lp->bus == PCI) {
4037 if (lp->chipset == DC21040) {
4045 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4046 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4048 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4049 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4062 if (lp->bus == PCI) {
4063 if (lp->chipset == DC21040) {
4109 de4x5_bad_srom(struct de4x5_private *lp)
4114 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4115 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4143 struct de4x5_private *lp = netdev_priv(dev);
4147 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4148 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4149 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4150 lp->useSROM = true;
4162 struct de4x5_private *lp = netdev_priv(dev);
4167 if ((lp->chipset == last.chipset) &&
4168 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4175 if (!an_exception(lp)) {
4182 last.chipset = lp->chipset;
4183 last.bus = lp->bus_num;
4195 an_exception(struct de4x5_private *lp)
4197 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4198 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4305 struct de4x5_private *lp = netdev_priv(dev);
4311 if (lp->chipset == infoleaf_array[i].chipset) break;
4314 lp->useSROM = false;
4320 lp->infoleaf_fn = infoleaf_array[i].fn;
4323 count = *((u_char *)&lp->srom + 19);
4324 p = (u_char *)&lp->srom + 26;
4328 if (lp->device == *p) break;
4331 lp->useSROM = false;
4333 dev->name, lp->device);
4338 lp->infoleaf_offset = get_unaligned_le16(p + 1);
4353 struct de4x5_private *lp = netdev_priv(dev);
4354 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4358 if (lp->chipset == DC21140) {
4359 lp->cache.gepc = (*p++ | GEP_CTRL);
4360 gep_wr(lp->cache.gepc, dev);
4396 struct de4x5_private *lp = netdev_priv(dev);
4401 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4403 if (lp->chipset != DC21140) RESET_SIA;
4406 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4411 if (lp->chipset != DC21140) {
4412 outl(lp->cache.csr14, DE4X5_STRR);
4413 outl(lp->cache.csr13, DE4X5_SICR);
4431 struct de4x5_private *lp = netdev_priv(dev);
4433 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4440 lp->cache.gepc = (*p++ | GEP_CTRL);
4452 if (lp->tcount == count) {
4453 lp->media = NC;
4454 if (lp->media != lp->c_media) {
4456 lp->c_media = lp->media;
4458 lp->media = INIT;
4459 lp->tcount = 0;
4460 lp->tx_enable = false;
4469 struct de4x5_private *lp = netdev_priv(dev);
4471 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4487 if (lp->tcount == count) {
4488 lp->media = NC;
4489 if (lp->media != lp->c_media) {
4491 lp->c_media = lp->media;
4493 lp->media = INIT;
4494 lp->tcount = 0;
4495 lp->tx_enable = false;
4504 struct de4x5_private *lp = netdev_priv(dev);
4506 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4521 if (lp->tcount == count) {
4522 lp->media = NC;
4523 if (lp->media != lp->c_media) {
4525 lp->c_media = lp->media;
4527 lp->media = INIT;
4528 lp->tcount = 0;
4529 lp->tx_enable = false;
4542 struct de4x5_private *lp = netdev_priv(dev);
4546 if (--count > lp->tcount) {
4554 if ((lp->media == INIT) && (lp->timeout < 0)) {
4555 lp->ibn = COMPACT;
4556 lp->active = 0;
4557 gep_wr(lp->cache.gepc, dev);
4558 lp->infoblock_media = (*p++) & COMPACT_MC;
4559 lp->cache.gep = *p++;
4563 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4564 lp->defMedium = (flags & 0x40) ? -1 : 0;
4565 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4566 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4567 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4568 lp->useMII = false;
4582 struct de4x5_private *lp = netdev_priv(dev);
4586 if (--count > lp->tcount) {
4594 if ((lp->media == INIT) && (lp->timeout < 0)) {
4595 lp->ibn = 0;
4596 lp->active = 0;
4597 gep_wr(lp->cache.gepc, dev);
4599 lp->infoblock_media = (*p++) & BLOCK0_MC;
4600 lp->cache.gep = *p++;
4604 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4605 lp->defMedium = (flags & 0x40) ? -1 : 0;
4606 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4607 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4608 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4609 lp->useMII = false;
4622 struct de4x5_private *lp = netdev_priv(dev);
4626 if (--count > lp->tcount) {
4635 if (lp->state == INITIALISED) {
4636 lp->ibn = 1;
4637 lp->active = *p++;
4638 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4639 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4640 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4641 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4642 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4643 lp->phy[lp->active].ttm = get_unaligned_le16(p);
4645 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4646 lp->ibn = 1;
4647 lp->active = *p;
4648 lp->infoblock_csr6 = OMR_MII_100;
4649 lp->useMII = true;
4650 lp->infoblock_media = ANS;
4661 struct de4x5_private *lp = netdev_priv(dev);
4665 if (--count > lp->tcount) {
4673 if ((lp->media == INIT) && (lp->timeout < 0)) {
4674 lp->ibn = 2;
4675 lp->active = 0;
4677 lp->infoblock_media = (*p) & MEDIA_CODE;
4680 lp->cache.csr13 = get_unaligned_le16(p); p += 2;
4681 lp->cache.csr14 = get_unaligned_le16(p); p += 2;
4682 lp->cache.csr15 = get_unaligned_le16(p); p += 2;
4684 lp->cache.csr13 = CSR13;
4685 lp->cache.csr14 = CSR14;
4686 lp->cache.csr15 = CSR15;
4688 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4689 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16);
4690 lp->infoblock_csr6 = OMR_SIA;
4691 lp->useMII = false;
4702 struct de4x5_private *lp = netdev_priv(dev);
4706 if (--count > lp->tcount) {
4715 if (lp->state == INITIALISED) {
4716 lp->ibn = 3;
4717 lp->active = *p++;
4718 if (MOTO_SROM_BUG) lp->active = 0;
4719 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4720 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4721 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4722 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4723 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4724 lp->phy[lp->active].ttm = get_unaligned_le16(p); p += 2;
4725 lp->phy[lp->active].mci = *p;
4727 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4728 lp->ibn = 3;
4729 lp->active = *p;
4730 if (MOTO_SROM_BUG) lp->active = 0;
4731 lp->infoblock_csr6 = OMR_MII_100;
4732 lp->useMII = true;
4733 lp->infoblock_media = ANS;
4744 struct de4x5_private *lp = netdev_priv(dev);
4748 if (--count > lp->tcount) {
4756 if ((lp->media == INIT) && (lp->timeout < 0)) {
4757 lp->ibn = 4;
4758 lp->active = 0;
4760 lp->infoblock_media = (*p++) & MEDIA_CODE;
4761 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4762 lp->cache.csr14 = CSR14;
4763 lp->cache.csr15 = CSR15;
4764 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4765 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4769 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4770 lp->defMedium = (flags & 0x40) ? -1 : 0;
4771 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4772 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4773 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4774 lp->useMII = false;
4789 struct de4x5_private *lp = netdev_priv(dev);
4793 if (--count > lp->tcount) {
4802 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4804 lp->rst = p;
4805 srom_exec(dev, lp->rst);
4979 struct de4x5_private *lp = netdev_priv(dev);
4984 lp->active = 0;
4985 lp->useMII = true;
4988 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
4989 lp->phy[lp->active].addr = i;
4996 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
4998 memcpy((char *)&lp->phy[k],
5000 lp->phy[k].addr = i;
5001 lp->mii_cnt++;
5002 lp->active++;
5009 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
5010 lp->phy[k].addr = i;
5011 lp->phy[k].id = id;
5012 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5013 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5014 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5015 lp->mii_cnt++;
5016 lp->active++;
5026 lp->active = 0;
5027 if (lp->phy[0].id) { /* Reset the PHY devices */
5028 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++) { /*For each PHY*/
5029 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5030 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5035 if (!lp->mii_cnt) lp->useMII = false;
5037 return lp->mii_cnt;
5043 struct de4x5_private *lp = netdev_priv(dev);
5045 char *pa = lp->setup_frame;
5049 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5052 if (lp->setup_f == HASH_PERF) {
5053 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5057 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5075 struct de4x5_private *lp = netdev_priv(dev);
5076 del_timer_sync(&lp->timer);
5082 struct de4x5_private *lp = netdev_priv(dev);
5091 omr |= lp->infoblock_csr6;
5099 if (lp->chipset == DC21140) {
5100 gep_wr(lp->cache.gepc, dev);
5101 gep_wr(lp->cache.gep, dev);
5102 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5103 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5118 struct de4x5_private *lp = netdev_priv(dev);
5121 if (lp->chipset == DC21140) {
5123 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5124 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5131 struct de4x5_private *lp = netdev_priv(dev);
5134 if (lp->chipset == DC21140) {
5136 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5146 struct de4x5_private *lp = netdev_priv(dev);
5149 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5151 if(lp->bus == EISA) {
5168 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5190 struct de4x5_private *lp = netdev_priv(dev);
5193 lp->params.fdx = false;
5194 lp->params.autosense = AUTO;
5203 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = true;
5207 lp->params.autosense = TP;
5209 lp->params.autosense = TP_NW;
5211 lp->params.autosense = BNC;
5213 lp->params.autosense = AUI;
5215 lp->params.autosense = BNC;
5217 lp->params.autosense = _10Mb;
5219 lp->params.autosense = _100Mb;
5221 lp->params.autosense = AUTO;
5231 struct de4x5_private *lp = netdev_priv(dev);
5238 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5240 for (i=0;i<lp->rxRingSize-1;i++){
5242 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5245 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5247 for (i=0;i<lp->txRingSize-1;i++){
5249 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5252 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5254 for (i=0;i<lp->rxRingSize-1;i++){
5256 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5259 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5261 for (i=0;i<lp->txRingSize-1;i++){
5263 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5266 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5268 (short)lp->rxRingSize,
5269 (short)lp->txRingSize);
5276 struct de4x5_private *lp = netdev_priv(dev);
5280 printk("\nMII device address: %d\n", lp->phy[k].addr);
5281 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5282 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5283 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5284 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5285 if (lp->phy[k].id != BROADCOM_T4) {
5286 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5287 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5289 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5290 if (lp->phy[k].id != BROADCOM_T4) {
5291 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5292 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5294 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5302 struct de4x5_private *lp = netdev_priv(dev);
5304 if (lp->media != lp->c_media) {
5307 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5308 (lp->media == TP ? "TP" :
5309 (lp->media == ANS ? "TP/Nway" :
5310 (lp->media == BNC ? "BNC" :
5311 (lp->media == AUI ? "AUI" :
5312 (lp->media == BNC_AUI ? "BNC/AUI" :
5313 (lp->media == EXT_SIA ? "EXT SIA" :
5314 (lp->media == _100Mb ? "100Mb/s" :
5315 (lp->media == _10Mb ? "10Mb/s" :
5317 ))))))))), (lp->fdx?" full duplex.":"."));
5319 lp->c_media = lp->media;
5372 struct de4x5_private *lp = netdev_priv(dev);
5404 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5406 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
5427 spin_lock_irqsave(&lp->lock, flags);
5428 memcpy(&statbuf, &lp->pktStats, ioc->len);
5429 spin_unlock_irqrestore(&lp->lock, flags);
5436 spin_lock_irqsave(&lp->lock, flags);
5437 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5438 spin_unlock_irqrestore(&lp->lock, flags);
5475 tmp.addr[j++] = lp->rxRingSize;
5476 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5477 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5479 for (i=0;i<lp->rxRingSize-1;i++){
5481 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5484 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5485 for (i=0;i<lp->txRingSize-1;i++){
5487 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5490 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5492 for (i=0;i<lp->rxRingSize-1;i++){
5494 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5497 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5498 for (i=0;i<lp->txRingSize-1;i++){
5500 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5503 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5505 for (i=0;i<lp->rxRingSize;i++){
5506 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5508 for (i=0;i<lp->txRingSize;i++){
5509 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5520 tmp.lval[j>>2] = lp->chipset; j+=4;
5521 if (lp->chipset == DC21140) {
5529 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5530 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5531 tmp.lval[j>>2] = lp->active; j+=4;
5532 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5533 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5534 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5535 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5536 if (lp->phy[lp->active].id != BROADCOM_T4) {
5537 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5538 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5540 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5541 if (lp->phy[lp->active].id != BROADCOM_T4) {
5542 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5543 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5545 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5549 tmp.addr[j++] = lp->txRingSize;