Lines Matching refs:csr0
87 static int csr0 = 0x01A00000 | 0xE000;
89 static int csr0 = 0x01A00000 | 0x8000;
95 static int csr0 = 0x01A00000 | 0x9000;
97 static int csr0 = 0x01A00000 | 0x4800;
99 static int csr0 = 0x00200000 | 0x4000;
102 static int csr0 = 0x00A00000 | 0x4800;
117 module_param(csr0, int, 0);
326 iowrite32(tp->csr0, ioaddr + CSR0);
1199 u32 csr0;
1204 tp->csr0 = csr0 = 0;
1207 csr0 |= MRM | MWI;
1216 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1217 csr0 &= ~MWI;
1221 if ((csr0 & MWI) && (cache == 0)) {
1222 csr0 &= ~MWI;
1231 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1234 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1237 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1245 * csr0, so save it and exit
1250 /* we don't have a good csr0 or cache line size, disable MWI */
1251 if (csr0 & MWI) {
1253 csr0 &= ~MWI;
1259 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1262 tp->csr0 = csr0;
1264 netdev_dbg(dev, "MWI config cacheline=%d, csr0=%08x\n",
1265 cache, csr0);
1384 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1390 if ((csr0 & 0x3f00) == 0)
1391 csr0 |= 0x2000;
1396 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1400 csr0 &= ~0x01f100ff;
1402 csr0 = (csr0 & ~0xff00) | 0xe000;
1476 tp->csr0 = csr0;