Lines Matching refs:phy
82 struct e1000_phy_info *phy = &hw->phy;
86 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
90 phy->id = (u32)(phy_id << 16);
92 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
96 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
97 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
113 if (!(hw->phy.ops.write_reg))
116 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
120 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
137 struct e1000_phy_info *phy = &hw->phy;
152 (phy->addr << E1000_MDIC_PHY_SHIFT) |
193 struct e1000_phy_info *phy = &hw->phy;
209 (phy->addr << E1000_MDIC_PHY_SHIFT) |
250 struct e1000_phy_info *phy = &hw->phy;
258 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
295 struct e1000_phy_info *phy = &hw->phy;
300 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
302 hw->phy.addr);
314 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
406 if (!(hw->phy.ops.acquire))
409 ret_val = hw->phy.ops.acquire(hw);
418 hw->phy.ops.release(hw);
426 hw->phy.ops.release(hw);
445 if (!(hw->phy.ops.acquire))
448 ret_val = hw->phy.ops.acquire(hw);
457 hw->phy.ops.release(hw);
465 hw->phy.ops.release(hw);
479 struct e1000_phy_info *phy = &hw->phy;
483 if (phy->reset_disable) {
488 if (phy->type == e1000_phy_82580) {
489 ret_val = hw->phy.ops.reset(hw);
497 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
506 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
511 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
520 switch (hw->phy.mdix) {
531 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
546 struct e1000_phy_info *phy = &hw->phy;
550 if (phy->reset_disable) {
556 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
571 switch (phy->mdix) {
594 if (phy->disable_polarity_correction == 1)
597 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
601 if (phy->revision < E1000_REVISION_4) {
605 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
612 if ((phy->revision == E1000_REVISION_2) &&
613 (phy->id == M88E1111_I_PHY_ID)) {
624 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
650 struct e1000_phy_info *phy = &hw->phy;
654 if (phy->reset_disable)
658 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
671 switch (phy->mdix) {
680 if (phy->id != M88E1112_E_PHY_ID) {
697 if (phy->disable_polarity_correction == 1)
701 if (phy->id == M88E1543_E_PHY_ID) {
704 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
719 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
745 struct e1000_phy_info *phy = &hw->phy;
749 if (phy->reset_disable) {
754 ret_val = phy->ops.reset(hw);
768 if (phy->type == e1000_phy_igp) {
770 if (phy->ops.set_d3_lplu_state)
771 ret_val = phy->ops.set_d3_lplu_state(hw, false);
779 ret_val = phy->ops.set_d0_lplu_state(hw, false);
785 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
791 switch (phy->mdix) {
803 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
813 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
815 ret_val = phy->ops.read_reg(hw,
822 ret_val = phy->ops.write_reg(hw,
829 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
834 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
839 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
844 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
850 switch (phy->ms_type) {
863 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
883 struct e1000_phy_info *phy = &hw->phy;
890 phy->autoneg_advertised &= phy->autoneg_mask;
895 if (phy->autoneg_advertised == 0)
896 phy->autoneg_advertised = phy->autoneg_mask;
909 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
914 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
921 if (phy->autoneg_wait_to_complete) {
946 struct e1000_phy_info *phy = &hw->phy;
951 phy->autoneg_advertised &= phy->autoneg_mask;
954 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
958 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
960 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
983 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
986 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
992 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
998 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1004 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1010 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1014 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1074 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1080 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1081 ret_val = phy->ops.write_reg(hw,
1118 ret_val = hw->phy.ops.force_speed_duplex(hw);
1154 struct e1000_phy_info *phy = &hw->phy;
1159 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1165 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1172 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1179 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1187 if (phy->autoneg_wait_to_complete) {
1188 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1219 struct e1000_phy_info *phy = &hw->phy;
1225 if (phy->type != e1000_phy_i210) {
1229 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1235 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1243 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1249 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1253 /* Reset the phy to commit changes. */
1258 if (phy->autoneg_wait_to_complete) {
1259 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1268 switch (hw->phy.id) {
1275 if (hw->phy.type != e1000_phy_m88)
1285 ret_val = phy->ops.write_reg(hw,
1303 if (hw->phy.type != e1000_phy_m88 ||
1304 hw->phy.id == I347AT4_E_PHY_ID ||
1305 hw->phy.id == M88E1112_E_PHY_ID ||
1306 hw->phy.id == I210_I_PHY_ID)
1309 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1313 /* Resetting the phy means we need to re-force TX_CLK in the
1318 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1325 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1330 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1365 /* Disable autoneg on the phy */
1413 struct e1000_phy_info *phy = &hw->phy;
1417 if (!(hw->phy.ops.read_reg))
1420 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1426 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1435 if (phy->smart_speed == e1000_smart_speed_on) {
1436 ret_val = phy->ops.read_reg(hw,
1443 ret_val = phy->ops.write_reg(hw,
1448 } else if (phy->smart_speed == e1000_smart_speed_off) {
1449 ret_val = phy->ops.read_reg(hw,
1456 ret_val = phy->ops.write_reg(hw,
1462 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1463 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1464 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1466 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1472 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1478 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1496 struct e1000_phy_info *phy = &hw->phy;
1500 switch (phy->type) {
1515 phy->speed_downgraded = false;
1520 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1523 phy->speed_downgraded = (phy_data & mask) ? true : false;
1539 struct e1000_phy_info *phy = &hw->phy;
1543 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1546 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1564 struct e1000_phy_info *phy = &hw->phy;
1571 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1587 ret_val = phy->ops.read_reg(hw, offset, &data);
1590 phy->cable_polarity = (data & mask)
1612 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1615 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1649 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1660 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1693 struct e1000_phy_info *phy = &hw->phy;
1697 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1708 phy->min_cable_length = e1000_m88_cable_length_table[index];
1709 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1711 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1719 struct e1000_phy_info *phy = &hw->phy;
1723 switch (hw->phy.id) {
1726 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1727 (I347AT4_PCDL + phy->addr),
1733 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1740 /* Populate the phy structure with cable length in meters */
1741 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1742 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1743 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1748 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1753 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
1758 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
1764 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
1770 /* Populate the phy structure with cable length in meters */
1771 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1772 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1773 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1776 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1783 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1788 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
1792 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
1804 phy->min_cable_length = e1000_m88_cable_length_table[index];
1805 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1807 phy->cable_length = (phy->min_cable_length +
1808 phy->max_cable_length) / 2;
1811 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1839 struct e1000_phy_info *phy = &hw->phy;
1853 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1888 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1890 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1892 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1910 struct e1000_phy_info *phy = &hw->phy;
1915 if (phy->media_type != e1000_media_type_copper) {
1931 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1935 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1942 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1946 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1949 ret_val = phy->ops.get_cable_length(hw);
1953 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
1957 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1961 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1966 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1967 phy->local_rx = e1000_1000t_rx_status_undefined;
1968 phy->remote_rx = e1000_1000t_rx_status_undefined;
1986 struct e1000_phy_info *phy = &hw->phy;
2001 phy->polarity_correction = true;
2007 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2011 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
2015 ret_val = phy->ops.get_cable_length(hw);
2019 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2023 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2027 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2031 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2032 phy->local_rx = e1000_1000t_rx_status_undefined;
2033 phy->remote_rx = e1000_1000t_rx_status_undefined;
2052 if (!(hw->phy.ops.read_reg))
2055 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2060 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2081 struct e1000_phy_info *phy = &hw->phy;
2091 ret_val = phy->ops.acquire(hw);
2099 udelay(phy->reset_delay_us);
2106 phy->ops.release(hw);
2108 ret_val = phy->ops.get_cfg_done(hw);
2126 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2128 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2130 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2132 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2134 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2136 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2138 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2140 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2142 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2144 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2146 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2148 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2150 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2152 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2154 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2156 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2158 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2160 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2162 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2164 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2166 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2168 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2170 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2172 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2174 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2176 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2180 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2182 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2186 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2188 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2190 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2192 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2209 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2211 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2226 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2228 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2242 struct e1000_phy_info *phy = &hw->phy;
2247 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2250 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY)
2267 struct e1000_phy_info *phy = &hw->phy;
2272 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2278 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2285 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
2291 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
2299 if (phy->autoneg_wait_to_complete) {
2300 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n");
2330 struct e1000_phy_info *phy = &hw->phy;
2345 phy->polarity_correction = true;
2351 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2355 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false;
2359 ret_val = hw->phy.ops.get_cable_length(hw);
2363 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2367 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2371 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2375 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2376 phy->local_rx = e1000_1000t_rx_status_undefined;
2377 phy->remote_rx = e1000_1000t_rx_status_undefined;
2393 struct e1000_phy_info *phy = &hw->phy;
2397 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data);
2407 phy->cable_length = length;
2429 ret_val = hw->phy.ops.acquire(hw);
2439 hw->phy.ops.release(hw);
2459 ret_val = hw->phy.ops.acquire(hw);
2469 hw->phy.ops.release(hw);
2485 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
2490 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
2495 switch (hw->phy.ms_type) {
2510 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);