Lines Matching refs:reg
46 u32 reg = 0;
51 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
52 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
54 reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
56 reg &= ~IXGBE_RMCS_ARBDIS;
58 reg |= IXGBE_RMCS_RRM;
60 reg |= IXGBE_RMCS_DFP;
62 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
69 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
72 reg |= IXGBE_RT2CR_LSP;
74 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
77 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
78 reg |= IXGBE_RDRXCTL_RDMTS_1_2;
79 reg |= IXGBE_RDRXCTL_MPBEN;
80 reg |= IXGBE_RDRXCTL_MCEN;
81 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
83 reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
85 reg &= ~IXGBE_RXCTRL_DMBYPS;
86 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
104 u32 reg, max_credits;
107 reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
110 reg &= ~IXGBE_DPMCS_ARBDIS;
111 reg |= IXGBE_DPMCS_TSOEF;
114 reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
116 IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
121 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
122 reg |= refill[i];
123 reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
126 reg |= IXGBE_TDTQ2TCCR_GSP;
129 reg |= IXGBE_TDTQ2TCCR_LSP;
131 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
150 u32 reg;
153 reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
155 reg &= ~IXGBE_PDPMCS_ARBDIS;
157 reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
159 IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
163 reg = refill[i];
164 reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
165 reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
168 reg |= IXGBE_TDPT2TCCR_GSP;
171 reg |= IXGBE_TDPT2TCCR_LSP;
173 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
177 reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
178 reg |= IXGBE_DTXCTL_ENDBUBD;
179 IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
193 u32 fcrtl, reg;
197 reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
198 reg &= ~IXGBE_RMCS_TFCE_802_3X;
199 reg |= IXGBE_RMCS_TFCE_PRIORITY;
200 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
203 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
204 reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);
207 reg |= IXGBE_FCTRL_RPFCE;
209 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
220 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
222 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
226 reg = hw->fc.pause_time * 0x00010001;
228 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
246 u32 reg = 0;
250 /* Receive Queues stats setting - 8 queues per statistics reg */
252 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
253 reg |= ((0x1010101) * j);
254 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
255 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
256 reg |= ((0x1010101) * j);
257 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
259 /* Transmit Queues stats setting - 4 queues per statistics reg */
261 reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
262 reg |= ((0x1010101) * i);
263 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);