Lines Matching refs:writel
41 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG);
57 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num));
61 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num));
65 writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num));
69 writel(upper_32_bits(dma_tx),
71 writel(lower_32_bits(dma_tx),
74 writel(upper_32_bits(dma_rx),
76 writel(lower_32_bits(dma_rx),
84 writel(lower_32_bits(dma_addr),
88 writel(lower_32_bits(dma_addr),
91 writel(t_rsize - 1, ioaddr + SXGBE_DMA_CHA_TXDESC_RINGLEN_REG(cha_num));
92 writel(r_rsize - 1, ioaddr + SXGBE_DMA_CHA_RXDESC_RINGLEN_REG(cha_num));
95 writel(SXGBE_DMA_ENA_INT,
105 writel(tx_config, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num));
111 writel(SXGBE_DMA_ENA_INT,
118 writel(0, ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(dma_cnum));
129 writel(tx_ctl_reg,
140 writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum));
149 writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum));
160 writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum));
172 writel(rx_ctl_reg,
185 writel(rx_ctl_reg, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum));
256 writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no));
322 writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no));
333 writel(riwt,
344 writel(ctrl, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(chan_num));