Lines Matching refs:eth
111 mace->eth.mac_addr = macaddr;
118 while ((___rval = mace->eth.phy_data) & MDIO_BUSY) { \
126 mace->eth.phy_regs = (priv->phy_addr << 5) | (phyreg & 0x1f);
128 mace->eth.phy_trans_go = 1;
197 mace->eth.mac_ctrl = priv->mac_ctrl;
206 mace->eth.mac_ctrl = priv->mac_ctrl;
220 mace->eth.tx_ring_base = priv->tx_ring_dma;
241 mace->eth.rx_fifo = priv->rx_ring_dmas[i];
279 mace->eth.mac_ctrl = SGI_MAC_RESET;
281 mace->eth.mac_ctrl = 0;
298 mace->eth.mac_ctrl = priv->mac_ctrl;
306 mace->eth.dma_ctrl = priv->dma_ctrl;
345 mace->eth.dma_ctrl = priv->dma_ctrl;
369 mace->eth.dma_ctrl = priv->dma_ctrl;
389 mace->eth.dma_ctrl = priv->dma_ctrl;
459 mace->eth.rx_fifo = priv->rx_ring_dmas[priv->rx_write];
465 mace->eth.dma_ctrl = priv->dma_ctrl;
466 mace->eth.int_stat = METH_INT_RX_THRESHOLD;
488 mace->eth.dma_ctrl = priv->dma_ctrl;
536 mace->eth.int_stat = METH_INT_TX_EMPTY | METH_INT_TX_PKT;
559 mace->eth.int_stat = METH_INT_RX_UNDERFLOW;
564 mace->eth.dma_ctrl = priv->dma_ctrl;
568 mace->eth.int_stat = METH_INT_ERROR;
580 status = mace->eth.int_stat;
599 status = mace->eth.int_stat;
693 mace->eth.tx_info = priv->tx_write;
708 mace->eth.dma_ctrl = priv->dma_ctrl;
721 mace->eth.dma_ctrl = priv->dma_ctrl;
754 mace->eth.dma_ctrl = priv->dma_ctrl;
804 mace->eth.mac_ctrl = priv->mac_ctrl;
805 mace->eth.mcast_filter = priv->mcast_filter;
840 dev->base_addr = (unsigned long)&mace->eth;
854 dev->name, (unsigned int)(mace->eth.mac_ctrl >> 29));