Lines Matching refs:fp
178 smc->hw.fp.fifo.rbc_ram_start = 0 ;
179 smc->hw.fp.fifo.rbc_ram_end =
180 smc->hw.fp.fifo.rbc_ram_start + RBC_MEM_SIZE ;
182 MARW(smc->hw.fp.fifo.rbc_ram_start) ;
183 for (i = smc->hw.fp.fifo.rbc_ram_start;
184 i < (u_short) (smc->hw.fp.fifo.rbc_ram_end-1); i++)
198 outpw(FM_A(FM_RPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* RPR1 */
199 outpw(FM_A(FM_SWPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* SWPR1 */
200 outpw(FM_A(FM_WPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* WPR1 */
201 outpw(FM_A(FM_EARV1),smc->hw.fp.fifo.tx_s_start-1) ; /* EARV1 */
206 if (smc->hw.fp.fifo.rx2_fifo_size) {
207 outpw(FM_A(FM_RPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
208 outpw(FM_A(FM_SWPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
209 outpw(FM_A(FM_WPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
210 outpw(FM_A(FM_EARV2),smc->hw.fp.fifo.rbc_ram_end-1) ;
213 outpw(FM_A(FM_RPR2),smc->hw.fp.fifo.rbc_ram_end-1) ;
214 outpw(FM_A(FM_SWPR2),smc->hw.fp.fifo.rbc_ram_end-1) ;
215 outpw(FM_A(FM_WPR2),smc->hw.fp.fifo.rbc_ram_end-1) ;
216 outpw(FM_A(FM_EARV2),smc->hw.fp.fifo.rbc_ram_end-1) ;
230 outpw(FM_A(FM_RPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* RPXA0 */
231 outpw(FM_A(FM_SWPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* SWPXA0 */
232 outpw(FM_A(FM_WPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* WPXA0 */
233 outpw(FM_A(FM_EAA0),smc->hw.fp.fifo.rx2_fifo_start-1) ; /* EAA0 */
238 if (smc->hw.fp.fifo.tx_s_size) {
239 outpw(FM_A(FM_RPXS),smc->hw.fp.fifo.tx_s_start) ;
240 outpw(FM_A(FM_SWPXS),smc->hw.fp.fifo.tx_s_start) ;
241 outpw(FM_A(FM_WPXS),smc->hw.fp.fifo.tx_s_start) ;
242 outpw(FM_A(FM_EAS),smc->hw.fp.fifo.tx_a0_start-1) ;
245 outpw(FM_A(FM_RPXS),smc->hw.fp.fifo.tx_a0_start-1) ;
246 outpw(FM_A(FM_SWPXS),smc->hw.fp.fifo.tx_a0_start-1) ;
247 outpw(FM_A(FM_WPXS),smc->hw.fp.fifo.tx_a0_start-1) ;
248 outpw(FM_A(FM_EAS),smc->hw.fp.fifo.tx_a0_start-1) ;
262 rbc_ram_addr = smc->hw.fp.fifo.rx2_fifo_start - 1 ;
283 smc->hw.fp.rx[QUEUE_R1] = queue = &smc->hw.fp.rx_q[QUEUE_R1] ;
290 smc->hw.fp.rx[QUEUE_R2] = queue = &smc->hw.fp.rx_q[QUEUE_R2] ;
313 smc->hw.fp.tx[QUEUE_S] = queue = &smc->hw.fp.tx_q[QUEUE_S] ;
324 smc->hw.fp.tx[QUEUE_A0] = queue = &smc->hw.fp.tx_q[QUEUE_A0] ;
346 ec = (u_long *)&smc->hw.fp.err_stats ;
369 outpw(FM_A(FM_LAGL),(unsigned short)((smc->hw.fp.group_addr.a[4]<<8) +
370 smc->hw.fp.group_addr.a[5])) ;
371 outpw(FM_A(FM_LAGC),(unsigned short)((smc->hw.fp.group_addr.a[2]<<8) +
372 smc->hw.fp.group_addr.a[3])) ;
373 outpw(FM_A(FM_LAGM),(unsigned short)((smc->hw.fp.group_addr.a[0]<<8) +
374 smc->hw.fp.group_addr.a[1])) ;
461 MARW(smc->hw.fp.fifo.rbc_ram_start+DBEACON_FRAME_OFF+4) ;
466 outpw(FM_A(FM_SABC),smc->hw.fp.fifo.rbc_ram_start + DBEACON_FRAME_OFF) ;
486 mac = &smc->hw.fp.mac_sfb ;
494 smc->hw.fp.fifo.rbc_ram_start + CLAIM_FRAME_OFF,len) ;
496 outpw(FM_A(FM_SACL),smc->hw.fp.fifo.rbc_ram_start + CLAIM_FRAME_OFF) ;
509 smc->hw.fp.fifo.rbc_ram_start + BEACON_FRAME_OFF,len) ;
511 outpw(FM_A(FM_SABC),smc->hw.fp.fifo.rbc_ram_start + BEACON_FRAME_OFF) ;
527 smc->hw.fp.fifo.rbc_ram_start + DBEACON_FRAME_OFF,len) ;
530 outpw(FM_A(FM_EACB),smc->hw.fp.fifo.rx1_fifo_start-1) ;
539 SETMASK(FM_A(FM_MDREG1),smc->hw.fp.rx_mode,FM_ADDRX) ;
698 change_s2l = smc->hw.fp.s2l ^ code_s2l ;
699 change_s2u = smc->hw.fp.s2u ^ code_s2u ;
764 smc->hw.fp.err_stats.err_bec_stat++ ;
766 smc->hw.fp.err_stats.err_clm_stat++ ;
770 if (!(change_s2l & FM_SRNGOP) && (smc->hw.fp.s2l & FM_SRNGOP)) {
780 smc->hw.fp.err_stats.err_phinv++ ;
782 smc->hw.fp.err_stats.err_sifg_det++ ;
784 smc->hw.fp.err_stats.err_tkiss++ ;
786 smc->hw.fp.err_stats.err_tkerr++ ;
798 smc->hw.fp.s2l = code_s2l ;
799 smc->hw.fp.s2u = code_s2u ;
851 smc->hw.fp.rx_mode, FM_MMODE | FM_SELRA | FM_ADDRX) ;
859 smc->hw.fp.nsa_mode = FM_MRNNSAFNMA ;
860 smc->hw.fp.rx_mode = FM_MDAMA ;
861 smc->hw.fp.group_addr = fddi_broadcast ;
862 smc->hw.fp.func_addr = 0 ;
863 smc->hw.fp.frselreg_init = 0 ;
867 smc->hw.fp.mdr3init |= FM_MENDAS ;
872 smc->hw.fp.fm_st1u = (HW_PTR) ADDR(B0_ST1U) ;
873 smc->hw.fp.fm_st1l = (HW_PTR) ADDR(B0_ST1L) ;
874 smc->hw.fp.fm_st2u = (HW_PTR) ADDR(B0_ST2U) ;
875 smc->hw.fp.fm_st2l = (HW_PTR) ADDR(B0_ST2L) ;
876 smc->hw.fp.fm_st3u = (HW_PTR) ADDR(B0_ST3U) ;
877 smc->hw.fp.fm_st3l = (HW_PTR) ADDR(B0_ST3L) ;
879 smc->hw.fp.s2l = smc->hw.fp.s2u = 0 ;
907 outpw(FM_A(FM_MDREG2),smc->hw.fp.mdr2init) ;
936 outpw(FM_A(FM_MDREG1),MDR1INIT | FM_SELRA | smc->hw.fp.rx_mode) ;
937 outpw(FM_A(FM_MDREG2),smc->hw.fp.mdr2init) ;
938 outpw(FM_A(FM_MDREG3),smc->hw.fp.mdr3init) ;
939 outpw(FM_A(FM_FRSELREG),smc->hw.fp.frselreg_init) ;
1080 for (i = 0, tb = smc->hw.fp.mc.table ; i < FPMAX_MULTICAST ; i++, tb++){
1109 smc->hw.fp.os_slots_used = 0 ; /* note the SMT addresses */
1111 for (i = 0, tb = smc->hw.fp.mc.table ; i < FPMAX_MULTICAST ; i++, tb++){
1155 if (smc->hw.fp.smt_slots_used >= SMT_MAX_MULTI) {
1160 if (smc->hw.fp.os_slots_used >= FPMAX_MULTICAST-SMT_MAX_MULTI) {
1175 smc->hw.fp.smt_slots_used++ ;
1177 smc->hw.fp.os_slots_used++ ;
1214 if (smc->hw.fp.func_addr) {
1215 fu = (u_char *) &smc->hw.fp.func_addr ;
1234 for (i = 0, tb = smc->hw.fp.mc.table; i < FPMAX_MULTICAST; i++, tb++) {
1280 smc->hw.fp.rx_prom |= RX_MODE_ALL_MULTI ;
1283 smc->hw.fp.rx_prom &= ~RX_MODE_ALL_MULTI ;
1286 smc->hw.fp.rx_prom |= RX_MODE_PROM ;
1289 smc->hw.fp.rx_prom &= ~RX_MODE_PROM ;
1292 smc->hw.fp.nsa_mode = FM_MDAMA ;
1293 smc->hw.fp.rx_mode = (smc->hw.fp.rx_mode & ~FM_ADDET) |
1294 smc->hw.fp.nsa_mode ;
1297 smc->hw.fp.nsa_mode = FM_MRNNSAFNMA ;
1298 smc->hw.fp.rx_mode = (smc->hw.fp.rx_mode & ~FM_ADDET) |
1299 smc->hw.fp.nsa_mode ;
1302 if (smc->hw.fp.rx_prom & RX_MODE_PROM) {
1303 smc->hw.fp.rx_mode = FM_MLIMPROM ;
1305 else if (smc->hw.fp.rx_prom & RX_MODE_ALL_MULTI) {
1306 smc->hw.fp.rx_mode = smc->hw.fp.nsa_mode | FM_EXGPA0 ;
1309 smc->hw.fp.rx_mode = smc->hw.fp.nsa_mode ;
1310 SETMASK(FM_A(FM_MDREG1),smc->hw.fp.rx_mode,FM_ADDRX) ;
1395 smc->hw.fp.fifo.rx1_fifo_size = RX_FIFO_SPACE ;
1396 smc->hw.fp.fifo.rx2_fifo_size = 0 ;
1401 smc->hw.fp.fifo.rx1_fifo_size = RX_LARGE_FIFO ;
1402 smc->hw.fp.fifo.rx2_fifo_size = RX_SMALL_FIFO ;
1405 smc->hw.fp.fifo.rx1_fifo_size = RX_FIFO_SPACE *
1407 smc->hw.fp.fifo.rx2_fifo_size = RX_FIFO_SPACE *
1436 smc->hw.fp.fifo.fifo_config_mode |=
1441 smc->hw.fp.fifo.fifo_config_mode &=
1448 if (smc->hw.fp.fifo.fifo_config_mode & SYNC_TRAFFIC_ON) {
1449 if (smc->hw.fp.fifo.fifo_config_mode & SEND_ASYNC_AS_SYNC) {
1450 smc->hw.fp.fifo.tx_s_size = TX_LARGE_FIFO ;
1451 smc->hw.fp.fifo.tx_a0_size = TX_SMALL_FIFO ;
1454 smc->hw.fp.fifo.tx_s_size = TX_MEDIUM_FIFO ;
1455 smc->hw.fp.fifo.tx_a0_size = TX_MEDIUM_FIFO ;
1459 smc->hw.fp.fifo.tx_s_size = 0 ;
1460 smc->hw.fp.fifo.tx_a0_size = TX_FIFO_SPACE ;
1463 smc->hw.fp.fifo.rx1_fifo_start = smc->hw.fp.fifo.rbc_ram_start +
1465 smc->hw.fp.fifo.tx_s_start = smc->hw.fp.fifo.rx1_fifo_start +
1466 smc->hw.fp.fifo.rx1_fifo_size ;
1467 smc->hw.fp.fifo.tx_a0_start = smc->hw.fp.fifo.tx_s_start +
1468 smc->hw.fp.fifo.tx_s_size ;
1469 smc->hw.fp.fifo.rx2_fifo_start = smc->hw.fp.fifo.tx_a0_start +
1470 smc->hw.fp.fifo.tx_a0_size ;
1472 DB_SMT("FIFO split: mode = %x\n",smc->hw.fp.fifo.fifo_config_mode,0) ;
1474 smc->hw.fp.fifo.rbc_ram_start, smc->hw.fp.fifo.rbc_ram_end) ;
1476 smc->hw.fp.fifo.rx1_fifo_start, smc->hw.fp.fifo.tx_s_start) ;
1478 smc->hw.fp.fifo.tx_a0_start, smc->hw.fp.fifo.rx2_fifo_start) ;
1488 if (!smc->hw.fp.fifo.tx_s_size && smc->mib.a[PATH0].fddiPATHSbaPayload){