Lines Matching refs:iobase
120 static int ali_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
138 static void SIR2FIR(int iobase);
139 static void FIR2SIR(int iobase);
331 IRDA_WARNING("%s(), can't get iobase of 0x%03x\n", __func__,
422 int iobase;
428 iobase = self->io.fir_base;
559 int iobase = info->fir_base;
569 SIR2FIR(iobase);
572 outb(0x40, iobase+FIR_MCR); // benjamin 2000/11/30 11:45AM
575 switch_bank(iobase, BANK3);
576 version = inb(iobase+FIR_ID_VR);
587 switch_bank(iobase, BANK1);
588 outb(RX_FIFO_Threshold, iobase+FIR_FIFO_TR);
591 outb(RX_DMA_Threshold, iobase+FIR_DMA_TR);
594 switch_bank(iobase, BANK2);
595 outb(inb(iobase+FIR_IRDA_CR) | IRDA_CR_CRC, iobase+FIR_IRDA_CR);
600 switch_bank(iobase, BANK0);
602 tmp = inb(iobase+FIR_LCR_B);
606 outb(tmp, iobase+FIR_LCR_B);
609 outb(0x00, iobase+FIR_IER);
613 FIR2SIR(iobase);
619 // outb(UART_IER_RDI, iobase+UART_IER); //benjamin 2000/11/23 01:25PM
702 int iobase, tmp;
706 iobase = self->io.fir_base;
708 switch_bank(iobase, BANK0);
709 self->InterruptID = inb(iobase+FIR_IIR);
710 self->BusStatus = inb(iobase+FIR_BSR);
713 self->LineStatus = inb(iobase+FIR_LSR);
714 //self->ier = inb(iobase+FIR_IER); 2000/12/1 04:32PM
782 switch_bank(iobase, BANK1);
783 tmp = inb(iobase+FIR_CR);
784 outb( tmp& ~CR_TIMER_EN, iobase+FIR_CR);
823 int iobase;
828 iobase = self->io.sir_base;
830 iir = inb(iobase+UART_IIR) & UART_IIR_ID;
833 lsr = inb(iobase+UART_LSR);
835 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n", __func__,
836 iir, lsr, iobase);
877 int iobase;
882 iobase = self->io.sir_base;
890 inb(iobase+UART_RX));
897 } while (inb(iobase+UART_LSR) & UART_LSR_DR);
912 int iobase;
918 iobase = self->io.sir_base;
924 actual = ali_ircc_sir_write(iobase, self->io.fifo_size,
934 while(!(inb(iobase+UART_LSR) & UART_LSR_TEMT))
959 outb(UART_IER_RDI, iobase+UART_IER);
968 int iobase;
977 iobase = self->io.fir_base;
1017 int iobase;
1026 iobase = self->io.fir_base;
1033 SIR2FIR(iobase);
1055 int iobase;
1066 iobase = self->io.sir_base;
1074 FIR2SIR(iobase);
1079 inb(iobase+UART_LSR);
1080 inb(iobase+UART_SCR);
1104 outb(UART_LCR_DLAB | lcr, iobase+UART_LCR); /* Set DLAB */
1105 outb(divisor & 0xff, iobase+UART_DLL); /* Set speed */
1106 outb(divisor >> 8, iobase+UART_DLM);
1107 outb(lcr, iobase+UART_LCR); /* Set 8N1 */
1108 outb(fcr, iobase+UART_FCR); /* Enable FIFO's */
1112 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), iobase+UART_MCR);
1123 int iobase,dongle_id;
1128 iobase = self->io.fir_base; /* or iobase = self->io.sir_base; */
1135 switch_bank(iobase, BANK2);
1136 tmp = inb(iobase+FIR_IRDA_CR);
1152 switch_bank(iobase, BANK2);
1153 outb(tmp, iobase+FIR_IRDA_CR);
1158 outb(tmp, iobase+FIR_IRDA_CR);
1164 outb(tmp, iobase+FIR_IRDA_CR);
1169 outb(tmp, iobase+FIR_IRDA_CR);
1175 outb(tmp, iobase+FIR_IRDA_CR);
1181 outb(tmp, iobase+FIR_IRDA_CR);
1185 outb(tmp & ~0x02, iobase+FIR_IRDA_CR);
1208 switch_bank(iobase, BANK2);
1209 outb(tmp, iobase+FIR_IRDA_CR);
1213 //switch_bank(iobase, BANK2);
1217 outb(tmp, iobase+FIR_IRDA_CR);
1223 outb(tmp, iobase+FIR_IRDA_CR);
1228 outb(tmp, iobase+FIR_IRDA_CR);
1232 outb(tmp & ~0x02, iobase+FIR_IRDA_CR);
1255 switch_bank(iobase, BANK2);
1256 outb(tmp, iobase+FIR_IRDA_CR);
1265 switch_bank(iobase, BANK2);
1266 outb(tmp, iobase+FIR_IRDA_CR);
1290 switch_bank(iobase, BANK2);
1291 outb(tmp, iobase+FIR_IRDA_CR);
1295 switch_bank(iobase, BANK0);
1306 static int ali_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1313 if (!(inb(iobase+UART_LSR) & UART_LSR_THRE)) {
1321 outb(buf[actual], iobase+UART_TX);
1339 int iobase;
1350 iobase = self->io.fir_base;
1374 outb(UART_IER_RDI , iobase+UART_IER);
1403 //int iobase;
1444 int iobase;
1451 iobase = self->io.fir_base;
1529 switch_bank(iobase, BANK1);
1530 outb(TIMER_IIR_500, iobase+FIR_TIMER_IIR);
1534 switch_bank(iobase, BANK1);
1535 outb(TIMER_IIR_1ms, iobase+FIR_TIMER_IIR);
1539 switch_bank(iobase, BANK1);
1540 outb(TIMER_IIR_2ms, iobase+FIR_TIMER_IIR);
1545 outb(inb(iobase+FIR_CR) | CR_TIMER_EN, iobase+FIR_CR);
1575 switch_bank(iobase, BANK0);
1588 int iobase, tmp;
1594 iobase = self->io.fir_base;
1604 switch_bank(iobase, BANK1);
1605 outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR);
1616 switch_bank(iobase, BANK0);
1617 outb(LCR_A_FIFO_RESET, iobase+FIR_LCR_A);
1622 switch_bank(iobase, BANK1);
1623 outb(FIFO_OPTI, iobase+FIR_FIFO_TR) ;
1628 switch_bank(iobase, BANK1);
1629 outb(TX_DMA_Threshold, iobase+FIR_DMA_TR);
1634 switch_bank(iobase, BANK2);
1635 outb(Hi, iobase+FIR_TX_DSR_HI);
1636 outb(Lo, iobase+FIR_TX_DSR_LO);
1639 switch_bank(iobase, BANK0);
1640 tmp = inb(iobase+FIR_LCR_B);
1642 outb(((unsigned char)(tmp & 0x3f) | LCR_B_TX_MODE) & ~LCR_B_BW, iobase+FIR_LCR_B);
1643 IRDA_DEBUG(1, "%s(), *** Change to TX mode: FIR_LCR_B = 0x%x ***\n", __func__ , inb(iobase+FIR_LCR_B));
1645 outb(0, iobase+FIR_LSR);
1648 switch_bank(iobase, BANK1);
1649 outb(inb(iobase+FIR_CR) | CR_DMA_EN | CR_DMA_BURST, iobase+FIR_CR);
1651 switch_bank(iobase, BANK0);
1658 int iobase;
1663 iobase = self->io.fir_base;
1666 switch_bank(iobase, BANK1);
1667 outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR);
1670 switch_bank(iobase, BANK0);
1671 if((inb(iobase+FIR_LSR) & LSR_FRAME_ABORT) == LSR_FRAME_ABORT)
1715 switch_bank(iobase, BANK0);
1730 int iobase, tmp;
1734 iobase = self->io.fir_base;
1741 switch_bank(iobase, BANK1);
1742 outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR);
1745 switch_bank(iobase, BANK0);
1746 outb(0x07, iobase+FIR_LSR);
1750 self->LineStatus = inb(iobase+FIR_LSR) ;
1757 // switch_bank(iobase, BANK0);
1758 outb(LCR_A_FIFO_RESET, iobase+FIR_LCR_A);
1767 //switch_bank(iobase, BANK0);
1768 tmp = inb(iobase+FIR_LCR_B);
1769 outb((unsigned char)(tmp &0x3f) | LCR_B_RX_MODE | LCR_B_BW , iobase + FIR_LCR_B); // 2000/12/1 05:16PM
1770 IRDA_DEBUG(1, "%s(), *** Change To RX mode: FIR_LCR_B = 0x%x ***\n", __func__ , inb(iobase+FIR_LCR_B));
1773 switch_bank(iobase, BANK1);
1774 outb(RX_FIFO_Threshold, iobase+FIR_FIFO_TR);
1775 outb(RX_DMA_Threshold, iobase+FIR_DMA_TR);
1778 // switch_bank(iobase, BANK1);
1779 outb(CR_DMA_EN | CR_DMA_BURST, iobase+FIR_CR);
1781 switch_bank(iobase, BANK0);
1791 int len, i, iobase, val;
1796 iobase = self->io.fir_base;
1798 switch_bank(iobase, BANK0);
1799 MessageCount = inb(iobase+ FIR_LSR)&0x07;
1807 switch_bank(iobase, BANK0);
1808 status = inb(iobase+FIR_LSR);
1810 switch_bank(iobase, BANK2);
1811 len = inb(iobase+FIR_RX_DSR_HI) & 0x0f;
1813 len |= inb(iobase+FIR_RX_DSR_LO);
1882 switch_bank(iobase, BANK0);
1883 val = inb(iobase+FIR_BSR);
1901 switch_bank(iobase, BANK1);
1902 outb(TIMER_IIR_500, iobase+FIR_TIMER_IIR); // 2001/1/2 05:07PM
1905 outb(inb(iobase+FIR_CR) | CR_TIMER_EN, iobase+FIR_CR);
1948 switch_bank(iobase, BANK0);
1967 int iobase;
1977 iobase = self->io.sir_base;
2012 outb(UART_IER_THRI, iobase+UART_IER);
2093 int iobase;
2103 iobase = self->io.fir_base;
2105 switch_bank(iobase, BANK1);
2106 if((inb(iobase+FIR_FIFO_FR) & 0x3f) != 0)
2112 switch_bank(iobase, BANK0);
2165 int iobase = self->io.fir_base; /* or sir_base */
2202 switch_bank(iobase, BANK0);
2203 outb(newMask, iobase+FIR_IER);
2206 outb(newMask, iobase+UART_IER);
2211 static void SIR2FIR(int iobase)
2220 outb(0x28, iobase+UART_MCR);
2221 outb(0x68, iobase+UART_MCR);
2222 outb(0x88, iobase+UART_MCR);
2224 outb(0x60, iobase+FIR_MCR); /* Master Reset */
2225 outb(0x20, iobase+FIR_MCR); /* Master Interrupt Enable */
2227 //tmp = inb(iobase+FIR_LCR_B); /* SIP enable */
2229 //outb(tmp, iobase+FIR_LCR_B);
2234 static void FIR2SIR(int iobase)
2243 outb(0x20, iobase+FIR_MCR); /* IRQ to low */
2244 outb(0x00, iobase+UART_IER);
2246 outb(0xA0, iobase+FIR_MCR); /* Don't set master reset */
2247 outb(0x00, iobase+UART_FCR);
2248 outb(0x07, iobase+UART_FCR);
2250 val = inb(iobase+UART_RX);
2251 val = inb(iobase+UART_LSR);
2252 val = inb(iobase+UART_MSR);