Lines Matching refs:ret
356 int ret;
358 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
359 if (ret < 0)
360 return ret;
362 ret |= 0x02;
363 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
370 int ret;
372 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
373 if (ret < 0)
374 return ret;
376 ret &= ~0x02;
377 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
384 int ret;
386 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
387 if (ret < 0)
388 return ret;
390 ret |= MDIO_CTRL1_LPOWER;
391 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
395 ret &= ~MDIO_CTRL1_LPOWER;
396 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
436 int ret;
439 ret = amd_xgbe_an_enable_kr_training(phydev);
440 if (ret < 0)
441 return ret;
444 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
445 if (ret < 0)
446 return ret;
448 ret &= ~MDIO_PCS_CTRL2_TYPE;
449 ret |= MDIO_PCS_CTRL2_10GBR;
450 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
452 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
453 if (ret < 0)
454 return ret;
456 ret &= ~MDIO_CTRL1_SPEEDSEL;
457 ret |= MDIO_CTRL1_SPEED10G;
458 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
460 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
461 if (ret < 0)
462 return ret;
484 int ret;
487 ret = amd_xgbe_an_disable_kr_training(phydev);
488 if (ret < 0)
489 return ret;
492 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
493 if (ret < 0)
494 return ret;
496 ret &= ~MDIO_PCS_CTRL2_TYPE;
497 ret |= MDIO_PCS_CTRL2_10GBX;
498 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
500 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
501 if (ret < 0)
502 return ret;
504 ret &= ~MDIO_CTRL1_SPEEDSEL;
505 ret |= MDIO_CTRL1_SPEED1G;
506 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
508 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
509 if (ret < 0)
510 return ret;
532 int ret;
535 ret = amd_xgbe_an_disable_kr_training(phydev);
536 if (ret < 0)
537 return ret;
540 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
541 if (ret < 0)
542 return ret;
544 ret &= ~MDIO_PCS_CTRL2_TYPE;
545 ret |= MDIO_PCS_CTRL2_10GBX;
546 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
548 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
549 if (ret < 0)
550 return ret;
552 ret &= ~MDIO_CTRL1_SPEEDSEL;
553 ret |= MDIO_CTRL1_SPEED1G;
554 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
556 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
557 if (ret < 0)
558 return ret;
580 int ret;
582 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
583 if (ret < 0)
584 return ret;
586 if ((ret & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)
607 int ret;
612 ret = amd_xgbe_phy_gmii_mode(phydev);
614 ret = amd_xgbe_phy_gmii_2500_mode(phydev);
616 ret = amd_xgbe_phy_xgmii_mode(phydev);
619 return ret;
626 int ret;
628 ret = amd_xgbe_phy_cur_mode(phydev, &cur_mode);
629 if (ret)
630 return ret;
633 ret = amd_xgbe_phy_switch_mode(phydev);
635 return ret;
642 int ad_reg, lp_reg, ret;
659 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL);
660 if (ret < 0)
664 ret |= 0x01;
666 ret &= ~0x01;
668 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL, ret);
671 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
672 if (ret < 0)
677 ret |= 0x01;
678 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
706 int ret, ad_reg, lp_reg;
709 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1);
710 if (ret < 0)
715 if (!(ret & link_support))
754 int ret;
768 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
769 if (ret < 0)
773 ret |= 0xc000;
775 ret &= ~0xc000;
777 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, ret);
780 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
781 if (ret < 0)
785 ret |= 0x80;
787 ret &= ~0x80;
791 ret |= 0x20;
793 ret &= ~0x20;
795 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, ret);
798 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
799 if (ret < 0)
803 ret |= 0x400;
805 ret &= ~0x400;
808 ret |= 0x800;
810 ret &= ~0x800;
813 ret &= ~XNP_NP_EXCHANGE;
815 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, ret);
820 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL);
821 if (ret < 0)
824 ret |= MDIO_KR_CTRL_PDETECT;
825 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL, ret);
827 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
828 if (ret < 0)
831 ret |= MDIO_AN_CTRL1_ENABLE;
832 ret |= MDIO_AN_CTRL1_RESTART;
833 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret);
841 int ret;
843 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT);
844 if (ret < 0)
848 if (ret & XGBE_AN_PG_RCV)
850 else if (ret & XGBE_AN_INC_LINK)
852 else if (ret & XGBE_AN_INT_CMPLT)
865 int ret;
872 ret = amd_xgbe_an_rx_bpa(phydev, state);
876 ret = amd_xgbe_an_rx_xnp(phydev, state);
880 ret = AMD_XGBE_AN_ERROR;
883 return ret;
888 int ret;
890 ret = amd_xgbe_phy_switch_mode(phydev);
891 if (ret)
975 int count, ret;
977 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
978 if (ret < 0)
979 return ret;
981 ret |= MDIO_CTRL1_RESET;
982 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
987 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
988 if (ret < 0)
989 return ret;
990 } while ((ret & MDIO_CTRL1_RESET) && --count);
992 if (ret & MDIO_CTRL1_RESET)
1027 int ret;
1030 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
1031 if (ret < 0)
1032 return ret;
1034 ret &= ~MDIO_AN_CTRL1_ENABLE;
1035 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret);
1040 ret = amd_xgbe_phy_xgmii_mode(phydev);
1044 ret = amd_xgbe_phy_gmii_2500_mode(phydev);
1048 ret = amd_xgbe_phy_gmii_mode(phydev);
1052 ret = -EINVAL;
1055 if (ret < 0)
1056 return ret;
1110 int ret;
1133 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
1134 if (ret < 0)
1135 return ret;
1137 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
1138 if (ret < 0)
1139 return ret;
1141 phydev->link = (ret & MDIO_STAT1_LSTATUS) ? 1 : 0;
1145 ret = amd_xgbe_phy_switch_mode(phydev);
1146 if (ret < 0)
1147 return ret;
1157 ret = amd_xgbe_phy_config_aneg(phydev);
1158 if (ret < 0)
1159 return ret;
1169 int ret, ad_ret, lp_ret;
1171 ret = amd_xgbe_phy_update_link(phydev);
1172 if (ret)
1173 return ret;
1207 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR);
1208 if (ret)
1209 return ret;
1221 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX);
1222 if (ret)
1223 return ret;
1251 int ret;
1255 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
1256 if (ret < 0)
1259 ret |= MDIO_CTRL1_LPOWER;
1260 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
1262 ret = 0;
1267 return ret;
1272 int ret;
1276 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
1277 if (ret < 0)
1280 ret &= ~MDIO_CTRL1_LPOWER;
1281 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
1283 ret = 0;
1288 return ret;
1299 int ret;
1311 ret = -ENOMEM;
1317 ret = -ENOMEM;
1330 ret = PTR_ERR(priv->rxtx_regs);
1338 ret = PTR_ERR(priv->sir0_regs);
1346 ret = PTR_ERR(priv->sir1_regs);
1366 ret = -EINVAL;
1376 ret = -ENOMEM;
1411 return ret;