Lines Matching defs:txq_id
1670 int txq_id;
1740 txq_id = skb_get_queue_mapping(skb);
1761 txq_id = il->stations[sta_id].tid[tid].agg.txq_id;
1766 txq = &il->txq[txq_id];
1800 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
1960 int txq_id;
1964 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1965 if (txq_id == il->cmd_queue)
1968 il_tx_queue_free(il, txq_id);
1988 int ret, txq_id;
2024 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
2025 ret = il_tx_queue_init(il, txq_id);
2027 IL_ERR("Tx %d queue init failed\n", txq_id);
2046 int txq_id;
2059 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2060 il_tx_queue_reset(il, txq_id);
2066 int txq_id;
2072 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2073 if (txq_id == il->cmd_queue)
2076 il_tx_queue_unmap(il, txq_id);
2112 int txq_id;
2114 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2115 if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk))
2116 return txq_id;
2124 il4965_tx_queue_stop_scheduler(struct il_priv *il, u16 txq_id)
2128 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
2137 il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid, u16 txq_id)
2146 il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
2150 if (txq_id & 0x1)
2163 * NOTE: txq_id must be greater than IL49_FIRST_AMPDU_QUEUE,
2167 il4965_txq_agg_enable(struct il_priv *il, int txq_id, int tx_fifo, int sta_id,
2174 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2176 il->cfg->num_of_ampdu_queues <= txq_id)) {
2178 txq_id, IL49_FIRST_AMPDU_QUEUE,
2194 il4965_tx_queue_stop_scheduler(il, txq_id);
2197 il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id);
2200 il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2204 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2205 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2206 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2211 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
2217 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
2222 il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2225 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1);
2238 int txq_id;
2263 txq_id = il4965_txq_ctx_activate_free(il);
2264 if (txq_id == -1) {
2272 tid_data->agg.txq_id = txq_id;
2273 il_set_swq_id(&il->txq[txq_id], il4965_get_ac_from_tid(tid), txq_id);
2276 ret = il4965_txq_agg_enable(il, txq_id, tx_fifo, sta_id, tid, *ssn);
2296 * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE
2300 il4965_txq_agg_disable(struct il_priv *il, u16 txq_id, u16 ssn_idx, u8 tx_fifo)
2302 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2304 il->cfg->num_of_ampdu_queues <= txq_id)) {
2306 txq_id, IL49_FIRST_AMPDU_QUEUE,
2312 il4965_tx_queue_stop_scheduler(il, txq_id);
2314 il_clear_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2316 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2317 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2319 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2321 il_clear_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2322 il_txq_ctx_deactivate(il, txq_id);
2323 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0);
2332 int tx_fifo_id, txq_id, sta_id, ssn;
2353 txq_id = tid_data->agg.txq_id;
2371 write_ptr = il->txq[txq_id].q.write_ptr;
2372 read_ptr = il->txq[txq_id].q.read_ptr;
2398 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id);
2407 il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id)
2409 struct il_queue *q = &il->txq[txq_id].q;
2419 if (txq_id == tid_data->agg.txq_id &&
2424 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo);
2472 il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
2474 struct il_tx_queue *txq = &il->txq[txq_id];
2482 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
2499 il4965_tx_status(il, skb, txq_id >= IL4965_FIRST_AMPDU_QUEUE);
2665 struct il4965_tx_resp *tx_resp, int txq_id,
2692 info = IEEE80211_SKB_CB(il->txq[txq_id].skbs[idx]);
2715 txq_id = SEQ_TO_QUEUE(seq);
2722 D_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
2723 agg->frame_count, txq_id, idx);
2725 skb = il->txq[txq_id].skbs[idx];
2780 int txq_id = SEQ_TO_QUEUE(sequence);
2782 struct il_tx_queue *txq = &il->txq[txq_id];
2795 IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
2796 "is out of range [0-%d] %d %d\n", txq_id, idx,
2840 il4965_tx_status_reply_tx(il, agg, tx_resp, txq_id, idx);
2851 freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2869 "rate_n_flags 0x%x retries %d\n", txq_id,
2874 freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2885 il4965_txq_check_empty(il, sta_id, tid, txq_id);
2950 if (unlikely(agg->txq_id != scd_flow)) {
2957 D_TX_REPLY("BA scd_flow %d does not match txq_id %d\n",
2958 scd_flow, agg->txq_id);
4019 int txq_id = txq->q.id;
4022 il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8);
6301 il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx)
6303 il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8));
6304 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx);
6311 int txq_id = txq->q.id;
6314 int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0;
6317 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
6327 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);