Lines Matching refs:hw
36 static u32 _rtl88e_phy_rf_serial_read(struct ieee80211_hw *hw,
38 static void _rtl88e_phy_rf_serial_write(struct ieee80211_hw *hw,
42 static bool _rtl88e_phy_bb8188e_config_parafile(struct ieee80211_hw *hw);
43 static bool _rtl88e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
44 static bool phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
46 static bool phy_config_bb_with_pghdr(struct ieee80211_hw *hw,
48 static void _rtl88e_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
53 static bool _rtl88e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
57 static long _rtl88e_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
60 static void rtl88ee_phy_set_rf_on(struct ieee80211_hw *hw);
61 static void rtl88e_phy_set_io(struct ieee80211_hw *hw);
63 u32 rtl88e_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
65 struct rtl_priv *rtlpriv = rtl_priv(hw);
82 void rtl88e_phy_set_bb_reg(struct ieee80211_hw *hw,
85 struct rtl_priv *rtlpriv = rtl_priv(hw);
105 u32 rtl88e_phy_query_rf_reg(struct ieee80211_hw *hw,
108 struct rtl_priv *rtlpriv = rtl_priv(hw);
119 original_value = _rtl88e_phy_rf_serial_read(hw, rfpath, regaddr);
131 void rtl88e_phy_set_rf_reg(struct ieee80211_hw *hw,
135 struct rtl_priv *rtlpriv = rtl_priv(hw);
146 original_value = _rtl88e_phy_rf_serial_read(hw,
155 _rtl88e_phy_rf_serial_write(hw, rfpath, regaddr, data);
165 static u32 _rtl88e_phy_rf_serial_read(struct ieee80211_hw *hw,
168 struct rtl_priv *rtlpriv = rtl_priv(hw);
178 if (RT_CANNOT_IO(hw)) {
182 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
186 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
189 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
192 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
195 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
198 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
201 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
204 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
212 static void _rtl88e_phy_rf_serial_write(struct ieee80211_hw *hw,
218 struct rtl_priv *rtlpriv = rtl_priv(hw);
222 if (RT_CANNOT_IO(hw)) {
229 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
246 bool rtl88e_phy_mac_config(struct ieee80211_hw *hw)
248 struct rtl_priv *rtlpriv = rtl_priv(hw);
249 bool rtstatus = _rtl88e_phy_config_mac_with_headerfile(hw);
255 bool rtl88e_phy_bb_config(struct ieee80211_hw *hw)
258 struct rtl_priv *rtlpriv = rtl_priv(hw);
262 _rtl88e_phy_init_bb_rf_register_definition(hw);
274 rtstatus = _rtl88e_phy_bb8188e_config_parafile(hw);
278 bool rtl88e_phy_rf_config(struct ieee80211_hw *hw)
280 return rtl88e_phy_rf6052_config(hw);
283 static bool _rtl88e_check_condition(struct ieee80211_hw *hw,
286 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
287 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
312 static void _rtl8188e_config_rf_reg(struct ieee80211_hw *hw, u32 addr,
329 rtl_set_rfreg(hw, rfpath, regaddr,
336 static void _rtl8188e_config_rf_radio_a(struct ieee80211_hw *hw,
342 _rtl8188e_config_rf_reg(hw, addr, data, RF90_PATH_A,
346 static void _rtl8188e_config_bb_reg(struct ieee80211_hw *hw,
362 rtl_set_bbreg(hw, addr, MASKDWORD, data);
367 static bool _rtl88e_phy_bb8188e_config_parafile(struct ieee80211_hw *hw)
369 struct rtl_priv *rtlpriv = rtl_priv(hw);
371 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
374 rtstatus = phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_PHY_REG);
383 phy_config_bb_with_pghdr(hw, BASEBAND_CONFIG_PHY_REG);
390 phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_AGC_TAB);
396 (bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200));
401 static bool _rtl88e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
403 struct rtl_priv *rtlpriv = rtl_priv(hw);
424 static void handle_branch1(struct ieee80211_hw *hw, u16 arraylen,
435 _rtl8188e_config_bb_reg(hw, v1, v2);
441 if (!_rtl88e_check_condition(hw, array_table[i])) {
456 _rtl8188e_config_bb_reg(hw, v1, v2);
466 static void handle_branch2(struct ieee80211_hw *hw, u16 arraylen,
469 struct rtl_priv *rtlpriv = rtl_priv(hw);
478 rtl_set_bbreg(hw, array_table[i], MASKDWORD,
487 if (!_rtl88e_check_condition(hw, array_table[i])) {
502 rtl_set_bbreg(hw, array_table[i],
519 static bool phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
528 handle_branch1(hw, arraylen, array_table);
532 handle_branch2(hw, arraylen, array_table);
537 static void store_pwrindex_rate_offset(struct ieee80211_hw *hw,
541 struct rtl_priv *rtlpriv = rtl_priv(hw);
667 static bool phy_config_bb_with_pghdr(struct ieee80211_hw *hw, u8 configtype)
669 struct rtl_priv *rtlpriv = rtl_priv(hw);
698 store_pwrindex_rate_offset(hw, phy_reg_page[i],
703 if (!_rtl88e_check_condition(hw,
738 static void process_path_a(struct ieee80211_hw *hw,
742 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
750 _rtl8188e_config_rf_radio_a(hw, v1, v2);
756 if (!_rtl88e_check_condition(hw, radioa_array_table[i])) {
774 _rtl8188e_config_rf_radio_a(hw, v1, v2);
786 _rtl8188e_config_rf_radio_a(hw, 0x52, 0x7E4BD);
789 bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
792 struct rtl_priv *rtlpriv = rtl_priv(hw);
805 process_path_a(hw, radioa_arraylen, radioa_array_table);
815 void rtl88e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
817 struct rtl_priv *rtlpriv = rtl_priv(hw);
821 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
823 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
825 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
827 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
836 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
838 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
846 static void _rtl88e_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
848 struct rtl_priv *rtlpriv = rtl_priv(hw);
932 void rtl88e_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
934 struct rtl_priv *rtlpriv = rtl_priv(hw);
940 txpwr_dbm = _rtl88e_phy_txpwr_idx_to_dbm(hw,
943 if (_rtl88e_phy_txpwr_idx_to_dbm(hw,
947 _rtl88e_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
950 if (_rtl88e_phy_txpwr_idx_to_dbm(hw,
954 _rtl88e_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
986 static void _rtl88e_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
990 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1015 static void _rtl88e_ccxpower_index_check(struct ieee80211_hw *hw,
1020 struct rtl_priv *rtlpriv = rtl_priv(hw);
1030 void rtl88e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
1032 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1040 _rtl88e_get_txpower_index(hw, channel,
1043 _rtl88e_ccxpower_index_check(hw, channel,
1046 rtl88e_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
1047 rtl88e_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0],
1052 static long _rtl88e_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
1075 void rtl88e_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1077 struct rtl_priv *rtlpriv = rtl_priv(hw);
1078 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1085 rtlpriv->cfg->ops->set_hw_reg(hw,
1092 rtlpriv->cfg->ops->set_hw_reg(hw,
1104 void rtl88e_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
1106 struct rtl_priv *rtlpriv = rtl_priv(hw);
1107 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1109 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1146 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1147 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1148 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);*/
1151 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1152 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1154 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
1156 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1157 /*rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);*/
1159 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1168 rtl88e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1173 void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw,
1176 struct rtl_priv *rtlpriv = rtl_priv(hw);
1178 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1184 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1185 rtl88e_phy_set_bw_mode_callback(hw);
1194 void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1196 struct rtl_priv *rtlpriv = rtl_priv(hw);
1197 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1209 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
1223 u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw)
1225 struct rtl_priv *rtlpriv = rtl_priv(hw);
1227 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1238 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1239 rtl88e_phy_sw_chnl_callback(hw);
1252 static bool _rtl88e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
1256 struct rtl_priv *rtlpriv = rtl_priv(hw);
1320 rtl88e_phy_set_txpower_level(hw, channel);
1340 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1383 static u8 _rtl88e_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
1388 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1c);
1389 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x30008c1c);
1390 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x8214032a);
1391 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160000);
1393 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1394 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1395 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1399 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1400 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1401 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1402 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1411 static u8 _rtl88e_phy_path_b_iqk(struct ieee80211_hw *hw)
1416 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1417 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1419 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1420 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1421 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1422 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1423 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1438 static u8 _rtl88e_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb)
1445 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1446 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
1447 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1448 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
1449 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);
1450 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1453 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1454 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x81004800);
1457 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1c);
1458 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x30008c1c);
1459 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160804);
1460 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000);
1463 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1465 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1466 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1470 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1471 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1472 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1484 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);
1487 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1488 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
1489 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1490 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
1491 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);
1492 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1495 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1498 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x30008c1c);
1499 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1c);
1500 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c05);
1501 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c05);
1504 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1506 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1507 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1511 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1512 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1513 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1514 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);
1523 static void _rtl88e_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
1533 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1539 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
1540 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
1546 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
1548 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
1550 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
1555 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1557 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1559 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1563 static void _rtl88e_phy_save_adda_registers(struct ieee80211_hw *hw,
1570 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1573 static void _rtl88e_phy_save_mac_registers(struct ieee80211_hw *hw,
1576 struct rtl_priv *rtlpriv = rtl_priv(hw);
1584 static void _rtl88e_phy_reload_adda_registers(struct ieee80211_hw *hw,
1591 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1594 static void _rtl88e_phy_reload_mac_registers(struct ieee80211_hw *hw,
1597 struct rtl_priv *rtlpriv = rtl_priv(hw);
1605 static void _rtl88e_phy_path_adda_on(struct ieee80211_hw *hw,
1614 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1616 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
1620 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);
1623 static void _rtl88e_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1626 struct rtl_priv *rtlpriv = rtl_priv(hw);
1637 static void _rtl88e_phy_path_a_standby(struct ieee80211_hw *hw)
1639 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1640 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1641 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1644 static void _rtl88e_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1649 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1650 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1653 static bool _rtl88e_phy_simularity_compare(struct ieee80211_hw *hw,
1657 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1713 static void _rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw,
1716 struct rtl_priv *rtlpriv = rtl_priv(hw);
1737 _rtl88e_phy_save_adda_registers(hw, adda_reg,
1739 _rtl88e_phy_save_mac_registers(hw, iqk_mac_reg,
1741 _rtl88e_phy_save_adda_registers(hw, iqk_bb_reg,
1745 _rtl88e_phy_path_adda_on(hw, adda_reg, true, is2t);
1748 (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1752 _rtl88e_phy_pi_mode_switch(hw, true);
1754 rtl_set_bbreg(hw, 0x800, BIT(24), 0x00);
1755 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1756 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1757 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1759 rtl_set_bbreg(hw, 0x870, BIT(10), 0x01);
1760 rtl_set_bbreg(hw, 0x870, BIT(26), 0x01);
1761 rtl_set_bbreg(hw, 0x860, BIT(10), 0x00);
1762 rtl_set_bbreg(hw, 0x864, BIT(10), 0x00);
1765 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1766 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1768 _rtl88e_phy_mac_setting_calibration(hw, iqk_mac_reg,
1770 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1772 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1774 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1775 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1776 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x81004800);
1778 patha_ok = _rtl88e_phy_path_a_iqk(hw, is2t);
1782 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1784 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1791 patha_ok = _rtl88e_phy_path_a_rx_iqk(hw, is2t);
1795 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1797 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1810 _rtl88e_phy_path_a_standby(hw);
1811 _rtl88e_phy_path_adda_on(hw, adda_reg, false, is2t);
1813 pathb_ok = _rtl88e_phy_path_b_iqk(hw);
1815 result[t][4] = (rtl_get_bbreg(hw,
1820 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1823 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1826 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1830 result[t][4] = (rtl_get_bbreg(hw,
1835 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1840 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1844 _rtl88e_phy_pi_mode_switch(hw, false);
1845 _rtl88e_phy_reload_adda_registers(hw, adda_reg,
1847 _rtl88e_phy_reload_mac_registers(hw, iqk_mac_reg,
1849 _rtl88e_phy_reload_adda_registers(hw, iqk_bb_reg,
1853 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1855 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1856 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
1857 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
1862 static void _rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1866 struct rtl_priv *rtlpriv = rtl_priv(hw);
1876 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
1879 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
1882 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
1886 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1889 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
1891 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
1897 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
1900 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1909 static void _rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1912 struct rtl_priv *rtlpriv = rtl_priv(hw);
1913 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1914 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1921 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1925 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1928 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1931 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0);
1932 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201);
1939 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
1941 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1944 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0);
1946 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
1948 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1951 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1);
1959 void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
1961 struct rtl_priv *rtlpriv = rtl_priv(hw);
1982 _rtl88e_phy_reload_adda_registers(hw,
2002 _rtl88e_phy_iq_calibrate(hw, result, i, true);
2004 _rtl88e_phy_iq_calibrate(hw, result, i, false);
2007 _rtl88e_phy_simularity_compare(hw, result, 0, 1);
2015 _rtl88e_phy_simularity_compare(hw, result, 0, 2);
2021 _rtl88e_phy_simularity_compare(hw, result, 1, 2);
2067 _rtl88e_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
2077 _rtl88e_phy_save_adda_registers(hw, iqk_bb_reg,
2081 void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw)
2083 struct rtl_priv *rtlpriv = rtl_priv(hw);
2098 _rtl88e_phy_lc_calibrate(hw, false);
2103 void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
2105 _rtl88e_phy_set_rfpath_switch(hw, bmain, false);
2108 bool rtl88e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2110 struct rtl_priv *rtlpriv = rtl_priv(hw);
2141 rtl88e_phy_set_io(hw);
2146 static void rtl88e_phy_set_io(struct ieee80211_hw *hw)
2148 struct rtl_priv *rtlpriv = rtl_priv(hw);
2158 /*rtl92c_dm_write_dig(hw);*/
2159 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel);
2160 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83);
2165 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40);
2177 static void rtl88ee_phy_set_rf_on(struct ieee80211_hw *hw)
2179 struct rtl_priv *rtlpriv = rtl_priv(hw);
2189 static void _rtl88ee_phy_set_rf_sleep(struct ieee80211_hw *hw)
2191 struct rtl_priv *rtlpriv = rtl_priv(hw);
2194 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2199 static bool _rtl88ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
2202 struct rtl_priv *rtlpriv = rtl_priv(hw);
2203 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2204 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2205 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2221 rtstatus = rtl_ps_enable_nic(hw);
2233 rtl88ee_phy_set_rf_on(hw);
2236 rtlpriv->cfg->ops->led_control(hw,
2239 rtlpriv->cfg->ops->led_control(hw,
2273 rtl_ps_disable_nic(hw);
2277 rtlpriv->cfg->ops->led_control(hw,
2280 rtlpriv->cfg->ops->led_control(hw,
2317 _rtl88ee_phy_set_rf_sleep(hw);
2331 bool rtl88e_phy_set_rf_power_state(struct ieee80211_hw *hw,
2334 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2340 bresult = _rtl88ee_phy_set_rf_power_state(hw, rfpwr_state);