Lines Matching defs:rtlpriv

91 	struct rtl_priv *rtlpriv = rtl_priv(hw);
96 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
97 rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
99 rtlpriv->dm.dm_initialgain_enable = 1;
100 rtlpriv->dm.dm_flag = 0;
101 rtlpriv->dm.disable_framebursting = 0;
102 rtlpriv->dm.thermalvalue = 0;
105 rtlpriv->phy.lck_inprogress = false;
110 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
111 rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
112 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
148 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
150 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
151 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
152 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
153 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
154 if (rtlpriv->cfg->mod_params->disable_watchdog)
156 rtlpriv->psc.reg_fwctrl_lps = 3;
157 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
163 if (rtlpriv->psc.reg_fwctrl_lps == 1)
164 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
165 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
166 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
167 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
168 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
171 rtlpriv->psc.low_power_enable = false;
173 rtlpriv->rtlhal.earlymode_enable = false;
176 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
177 if (!rtlpriv->rtlhal.pfirmware) {
178 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
183 rtlpriv->max_fw_size = 0x8000;
184 pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
185 err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
186 rtlpriv->io.dev, GFP_KERNEL, hw,
189 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
198 struct rtl_priv *rtlpriv = rtl_priv(hw);
200 if (rtlpriv->rtlhal.pfirmware) {
201 vfree(rtlpriv->rtlhal.pfirmware);
202 rtlpriv->rtlhal.pfirmware = NULL;