Cross Reference: /drivers/ntb/ntb

Lines Matching refs:reg_base
547 	writeb(0xe0, ndev->reg_base + BWD_MODPHY_PCSREG6);
548 	writeb(0x40, ndev->reg_base + BWD_MODPHY_PCSREG4);
549 	writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG4);
550 	writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG6);
556 	status = readl(ndev->reg_base + BWD_ERRCORSTS_OFFSET);
559 	writel(status, ndev->reg_base + BWD_ERRCORSTS_OFFSET);
562 	status = readl(ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
565 	writel(status, ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
568 	status = readl(ndev->reg_base + BWD_DESKEWSTS_OFFSET);
571 	writel(status, ndev->reg_base + BWD_DESKEWSTS_OFFSET);
573 	status = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
576 	writel(status, ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
579 	status = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
582 	writel(status, ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
672 	status32 = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
676 	status32 = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
717 			u32 status32 = readl(ndev->reg_base +
733 		ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
734 		ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
735 		ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
736 		ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
737 		ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
740 				ndev->reg_base + SNB_SBAR5XLAT_OFFSET;
764 			writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base +
781 			ndev->reg_ofs.spad_write = ndev->reg_base +
783 			ndev->reg_ofs.rdb = ndev->reg_base +
790 			writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET);
808 			writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
811 				writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
816 					       ndev->reg_base +
819 					       ndev->reg_base +
823 					       ndev->reg_base +
830 				       ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
832 				       ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
835 			writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
837 			writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
840 				writel(SNB_MBAR4_USD_ADDR, ndev->reg_base +
842 				writel(SNB_MBAR5_USD_ADDR, ndev->reg_base +
845 				writeq(SNB_MBAR4_USD_ADDR, ndev->reg_base +
848 			writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
851 				writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
856 					       ndev->reg_base +
859 					       ndev->reg_base +
863 					       ndev->reg_base +
871 				       ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
873 				       ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
875 			writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
877 			writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
880 				writel(SNB_MBAR4_DSD_ADDR, ndev->reg_base +
882 				writel(SNB_MBAR5_DSD_ADDR, ndev->reg_base +
885 				writeq(SNB_MBAR4_DSD_ADDR, ndev->reg_base +
906 		ndev->reg_ofs.rdb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
907 		ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
908 		ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
912 		ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET +
914 		ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
915 		ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
916 		ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
919 				ndev->reg_base + SNB_SBAR5XLAT_OFFSET;
937 		ndev->reg_ofs.rdb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
938 		ndev->reg_ofs.ldb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
939 		ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_SDBMSK_OFFSET;
940 		ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET;
944 		ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET +
946 		ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_PBAR2XLAT_OFFSET;
947 		ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_PBAR4XLAT_OFFSET;
951 				ndev->reg_base + SNB_PBAR5XLAT_OFFSET;
964 	ndev->reg_ofs.lnk_cntl = ndev->reg_base + SNB_NTBCNTL_OFFSET;
965 	ndev->reg_ofs.lnk_stat = ndev->reg_base + SNB_SLINK_STATUS_OFFSET;
966 	ndev->reg_ofs.spci_cmd = ndev->reg_base + SNB_PCICMD_OFFSET;
1006 	ndev->reg_ofs.ldb = ndev->reg_base + BWD_PDOORBELL_OFFSET;
1007 	ndev->reg_ofs.ldb_mask = ndev->reg_base + BWD_PDBMSK_OFFSET;
1008 	ndev->reg_ofs.rdb = ndev->reg_base + BWD_B2B_DOORBELL_OFFSET;
1009 	ndev->reg_ofs.bar2_xlat = ndev->reg_base + BWD_SBAR2XLAT_OFFSET;
1010 	ndev->reg_ofs.bar4_xlat = ndev->reg_base + BWD_SBAR4XLAT_OFFSET;
1011 	ndev->reg_ofs.lnk_cntl = ndev->reg_base + BWD_NTBCNTL_OFFSET;
1012 	ndev->reg_ofs.lnk_stat = ndev->reg_base + BWD_LINK_STATUS_OFFSET;
1013 	ndev->reg_ofs.spad_read = ndev->reg_base + BWD_SPAD_OFFSET;
1014 	ndev->reg_ofs.spad_write = ndev->reg_base + BWD_B2B_SPAD_OFFSET;
1015 	ndev->reg_ofs.spci_cmd = ndev->reg_base + BWD_PCICMD_OFFSET;
1478 				   readw(ndev->reg_base +
1748 	ndev->reg_base = pci_ioremap_bar(pdev, NTB_BAR_MMIO);
1749 	if (!ndev->reg_base) {
1840 	iounmap(ndev->reg_base);
1879 	iounmap(ndev->reg_base);