Lines Matching refs:hba
192 u8 first_bus = d->hba.hba_bus->busn_res.start;
193 u8 last_sub_bus = d->hba.hba_bus->busn_res.end;
208 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
211 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
217 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
223 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
229 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
238 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
243 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
248 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
253 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
308 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
311 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
316 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
348 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
350 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
359 LBA_CFG_RESTORE(d, d->hba.base_addr);
369 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
412 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
421 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
422 LBA_CFG_RESTORE(d, d->hba.base_addr);
457 case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
459 case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
461 case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
465 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
486 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
516 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
539 lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
705 ldev->hba.io_space.name,
706 ldev->hba.io_space.start, ldev->hba.io_space.end,
707 ldev->hba.io_space.flags);
709 ldev->hba.lmmio_space.name,
710 ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end,
711 ldev->hba.lmmio_space.flags);
713 err = request_resource(&ioport_resource, &(ldev->hba.io_space));
719 if (ldev->hba.elmmio_space.flags) {
721 &(ldev->hba.elmmio_space));
726 (long)ldev->hba.elmmio_space.start,
727 (long)ldev->hba.elmmio_space.end);
734 if (ldev->hba.lmmio_space.flags) {
735 err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space));
739 (long)ldev->hba.lmmio_space.start,
740 (long)ldev->hba.lmmio_space.end);
746 if (ldev->hba.gmmio_space.flags) {
747 err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space));
751 (long)ldev->hba.gmmio_space.start,
752 (long)ldev->hba.gmmio_space.end);
1037 lba_dev->hba.bus_num.start = p->start;
1038 lba_dev->hba.bus_num.end = p->end;
1039 lba_dev->hba.bus_num.flags = IORESOURCE_BUS;
1044 if (!lba_dev->hba.lmmio_space.flags) {
1047 lba_len = ~READ_REG32(lba_dev->hba.base_addr
1053 sprintf(lba_dev->hba.lmmio_name,
1055 (int)lba_dev->hba.bus_num.start);
1056 lba_dev->hba.lmmio_space_offset = p->start -
1058 r = &lba_dev->hba.lmmio_space;
1059 r->name = lba_dev->hba.lmmio_name;
1060 } else if (!lba_dev->hba.elmmio_space.flags) {
1061 sprintf(lba_dev->hba.elmmio_name,
1063 (int)lba_dev->hba.bus_num.start);
1064 r = &lba_dev->hba.elmmio_space;
1065 r->name = lba_dev->hba.elmmio_name;
1080 sprintf(lba_dev->hba.gmmio_name, "PCI%02x GMMIO",
1081 (int)lba_dev->hba.bus_num.start);
1082 r = &lba_dev->hba.gmmio_space;
1083 r->name = lba_dev->hba.gmmio_name;
1103 sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
1104 (int)lba_dev->hba.bus_num.start);
1105 r = &lba_dev->hba.io_space;
1106 r->name = lba_dev->hba.io_name;
1107 r->start = HBA_PORT_BASE(lba_dev->hba.hba_num);
1141 lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND;
1150 lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH);
1151 r = &(lba_dev->hba.bus_num);
1160 r = &(lba_dev->hba.lmmio_space);
1161 sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO",
1162 (int)lba_dev->hba.bus_num.start);
1163 r->name = lba_dev->hba.lmmio_name;
1232 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE);
1240 rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK);
1269 r = &(lba_dev->hba.elmmio_space);
1270 sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO",
1271 (int)lba_dev->hba.bus_num.start);
1272 r->name = lba_dev->hba.elmmio_name;
1278 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE);
1286 rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK);
1291 r = &(lba_dev->hba.io_space);
1292 sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
1293 (int)lba_dev->hba.bus_num.start);
1294 r->name = lba_dev->hba.io_name;
1296 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L;
1297 r->end = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1));
1300 lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num);
1326 d->hba.base_addr,
1327 READ_REG64(d->hba.base_addr + LBA_STAT_CTL),
1328 READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG),
1329 READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS),
1330 READ_REG64(d->hba.base_addr + LBA_DMA_CTL) );
1332 READ_REG64(d->hba.base_addr + LBA_ARB_MASK),
1333 READ_REG64(d->hba.base_addr + LBA_ARB_PRI),
1334 READ_REG64(d->hba.base_addr + LBA_ARB_MODE),
1335 READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) );
1337 READ_REG64(d->hba.base_addr + LBA_HINT_CFG));
1341 printk(" %Lx", READ_REG64(d->hba.base_addr + i));
1355 bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1;
1360 stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);
1364 WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG);
1368 stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);
1369 WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
1379 if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) {
1390 WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK);
1500 lba_dev->hba.base_addr = addr;
1501 lba_dev->hba.dev = dev;
1503 lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */
1532 if (lba_dev->hba.bus_num.start < lba_next_bus)
1533 lba_dev->hba.bus_num.start = lba_next_bus;
1545 &(lba_dev->hba.lmmio_space))) {
1547 (long)lba_dev->hba.lmmio_space.start,
1548 (long)lba_dev->hba.lmmio_space.end);
1549 lba_dev->hba.lmmio_space.flags = 0;
1552 pci_add_resource_offset(&resources, &lba_dev->hba.io_space,
1553 HBA_PORT_BASE(lba_dev->hba.hba_num));
1554 if (lba_dev->hba.elmmio_space.flags)
1555 pci_add_resource_offset(&resources, &lba_dev->hba.elmmio_space,
1556 lba_dev->hba.lmmio_space_offset);
1557 if (lba_dev->hba.lmmio_space.flags)
1558 pci_add_resource_offset(&resources, &lba_dev->hba.lmmio_space,
1559 lba_dev->hba.lmmio_space_offset);
1560 if (lba_dev->hba.gmmio_space.flags)
1561 pci_add_resource(&resources, &lba_dev->hba.gmmio_space);
1563 pci_add_resource(&resources, &lba_dev->hba.bus_num);
1566 lba_bus = lba_dev->hba.hba_bus =
1567 pci_create_root_bus(&dev->dev, lba_dev->hba.bus_num.start,
1588 lba_dump_res(&lba_dev->hba.io_space, 2);
1590 lba_dump_res(&lba_dev->hba.lmmio_space, 2);