Lines Matching refs:ctrl
44 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
46 return ctrl->pcie->port;
50 static void start_int_poll_timer(struct controller *ctrl, int sec);
55 struct controller *ctrl = (struct controller *)data;
58 pcie_isr(0, ctrl);
60 init_timer(&ctrl->poll_timer);
64 start_int_poll_timer(ctrl, pciehp_poll_time);
68 static void start_int_poll_timer(struct controller *ctrl, int sec)
74 ctrl->poll_timer.function = &int_poll_timeout;
75 ctrl->poll_timer.data = (unsigned long)ctrl;
76 ctrl->poll_timer.expires = jiffies + sec * HZ;
77 add_timer(&ctrl->poll_timer);
80 static inline int pciehp_request_irq(struct controller *ctrl)
82 int retval, irq = ctrl->pcie->irq;
86 init_timer(&ctrl->poll_timer);
87 start_int_poll_timer(ctrl, 10);
92 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
94 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
99 static inline void pciehp_free_irq(struct controller *ctrl)
102 del_timer_sync(&ctrl->poll_timer);
104 free_irq(ctrl->pcie->irq, ctrl);
107 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
109 struct pci_dev *pdev = ctrl_dev(ctrl);
131 static void pcie_wait_cmd(struct controller *ctrl)
135 unsigned long cmd_timeout = ctrl->cmd_started + duration;
143 if (NO_CMD_CMPL(ctrl))
146 if (!ctrl->cmd_busy)
159 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
160 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
161 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
163 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
174 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
175 ctrl->slot_ctrl,
176 jiffies_to_msecs(jiffies - ctrl->cmd_started));
181 * @ctrl: controller to which the command is issued
185 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
187 struct pci_dev *pdev = ctrl_dev(ctrl);
190 mutex_lock(&ctrl->ctrl_lock);
193 pcie_wait_cmd(ctrl);
198 ctrl->cmd_busy = 1;
201 ctrl->cmd_started = jiffies;
202 ctrl->slot_ctrl = slot_ctrl;
204 mutex_unlock(&ctrl->ctrl_lock);
207 bool pciehp_check_link_active(struct controller *ctrl)
209 struct pci_dev *pdev = ctrl_dev(ctrl);
217 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
222 static void __pcie_wait_link_active(struct controller *ctrl, bool active)
226 if (pciehp_check_link_active(ctrl) == active)
231 if (pciehp_check_link_active(ctrl) == active)
234 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
238 static void pcie_wait_link_active(struct controller *ctrl)
240 __pcie_wait_link_active(ctrl, true);
269 int pciehp_check_link_status(struct controller *ctrl)
271 struct pci_dev *pdev = ctrl_dev(ctrl);
280 if (ctrl->link_active_reporting)
281 pcie_wait_link_active(ctrl);
287 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
291 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
294 ctrl_err(ctrl, "Link Training Error occurs\n");
298 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
306 static int __pciehp_link_set(struct controller *ctrl, bool enable)
308 struct pci_dev *pdev = ctrl_dev(ctrl);
319 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
323 static int pciehp_link_enable(struct controller *ctrl)
325 return __pciehp_link_set(ctrl, true);
330 struct controller *ctrl = slot->ctrl;
331 struct pci_dev *pdev = ctrl_dev(ctrl);
335 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
336 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
356 struct controller *ctrl = slot->ctrl;
357 struct pci_dev *pdev = ctrl_dev(ctrl);
361 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
362 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
379 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
388 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
397 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
406 struct controller *ctrl = slot->ctrl;
409 if (!ATTN_LED(ctrl))
425 pcie_write_cmd(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
426 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
427 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
432 struct controller *ctrl = slot->ctrl;
434 if (!PWR_LED(ctrl))
437 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, PCI_EXP_SLTCTL_PIC);
438 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
439 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
445 struct controller *ctrl = slot->ctrl;
447 if (!PWR_LED(ctrl))
450 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, PCI_EXP_SLTCTL_PIC);
451 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
452 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
458 struct controller *ctrl = slot->ctrl;
460 if (!PWR_LED(ctrl))
463 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, PCI_EXP_SLTCTL_PIC);
464 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
465 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
471 struct controller *ctrl = slot->ctrl;
472 struct pci_dev *pdev = ctrl_dev(ctrl);
481 ctrl->power_fault_detected = 0;
483 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
484 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
485 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
488 retval = pciehp_link_enable(ctrl);
490 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
497 struct controller *ctrl = slot->ctrl;
499 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
500 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
501 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
507 struct controller *ctrl = (struct controller *)dev_id;
508 struct pci_dev *pdev = ctrl_dev(ctrl);
511 struct slot *slot = ctrl->slot;
535 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
539 ctrl->cmd_busy = 0;
541 wake_up(&ctrl->queue);
547 ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n",
570 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
571 ctrl->power_fault_detected = 1;
581 void pcie_enable_notification(struct controller *ctrl)
602 if (ATTN_BUTTN(ctrl))
606 if (MRL_SENS(ctrl))
616 pcie_write_cmd(ctrl, cmd, mask);
617 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
618 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
621 static void pcie_disable_notification(struct controller *ctrl)
629 pcie_write_cmd(ctrl, 0, mask);
630 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
631 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
644 struct controller *ctrl = slot->ctrl;
645 struct pci_dev *pdev = ctrl_dev(ctrl);
651 if (!ATTN_BUTTN(ctrl)) {
658 pcie_write_cmd(ctrl, 0, ctrl_mask);
659 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
660 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
662 del_timer_sync(&ctrl->poll_timer);
664 pci_reset_bridge_secondary_bus(ctrl->pcie->port);
667 pcie_write_cmd(ctrl, ctrl_mask, ctrl_mask);
668 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
669 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
671 int_poll_timeout(ctrl->poll_timer.data);
676 int pcie_init_notification(struct controller *ctrl)
678 if (pciehp_request_irq(ctrl))
680 pcie_enable_notification(ctrl);
681 ctrl->notification_enabled = 1;
685 static void pcie_shutdown_notification(struct controller *ctrl)
687 if (ctrl->notification_enabled) {
688 pcie_disable_notification(ctrl);
689 pciehp_free_irq(ctrl);
690 ctrl->notification_enabled = 0;
694 static int pcie_init_slot(struct controller *ctrl)
702 slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
706 slot->ctrl = ctrl;
710 ctrl->slot = slot;
717 static void pcie_cleanup_slot(struct controller *ctrl)
719 struct slot *slot = ctrl->slot;
725 static inline void dbg_ctrl(struct controller *ctrl)
729 struct pci_dev *pdev = ctrl->pcie->port;
734 ctrl_info(ctrl, "Hotplug Controller:\n");
735 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
737 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
738 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
739 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
741 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
743 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
748 ctrl_info(ctrl, " PCI resource [%d] : %pR\n",
751 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
752 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
753 ctrl_info(ctrl, " Attention Button : %3s\n",
754 ATTN_BUTTN(ctrl) ? "yes" : "no");
755 ctrl_info(ctrl, " Power Controller : %3s\n",
756 POWER_CTRL(ctrl) ? "yes" : "no");
757 ctrl_info(ctrl, " MRL Sensor : %3s\n",
758 MRL_SENS(ctrl) ? "yes" : "no");
759 ctrl_info(ctrl, " Attention Indicator : %3s\n",
760 ATTN_LED(ctrl) ? "yes" : "no");
761 ctrl_info(ctrl, " Power Indicator : %3s\n",
762 PWR_LED(ctrl) ? "yes" : "no");
763 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
764 HP_SUPR_RM(ctrl) ? "yes" : "no");
765 ctrl_info(ctrl, " EMI Present : %3s\n",
766 EMI(ctrl) ? "yes" : "no");
767 ctrl_info(ctrl, " Command Completed : %3s\n",
768 NO_CMD_CMPL(ctrl) ? "no" : "yes");
770 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
772 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
779 struct controller *ctrl;
783 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
784 if (!ctrl) {
788 ctrl->pcie = dev;
790 ctrl->slot_cap = slot_cap;
791 mutex_init(&ctrl->ctrl_lock);
792 init_waitqueue_head(&ctrl->queue);
793 dbg_ctrl(ctrl);
798 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
799 ctrl->link_active_reporting = 1;
808 ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n",
819 if (pcie_init_slot(ctrl))
822 return ctrl;
825 kfree(ctrl);
830 void pciehp_release_ctrl(struct controller *ctrl)
832 pcie_shutdown_notification(ctrl);
833 pcie_cleanup_slot(ctrl);
834 kfree(ctrl);