Lines Matching refs:phy
2 * phy-ti-pipe3 - PIPE3 PHY driver.
22 #include <linux/phy/phy.h>
29 #include <linux/phy/omap_control_phy.h>
119 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
122 struct pipe3_dpll_map *dpll_map = phy->dpll_map;
124 rate = clk_get_rate(phy->sys_clk);
131 dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
136 static int ti_pipe3_power_off(struct phy *x)
138 struct ti_pipe3 *phy = phy_get_drvdata(x);
140 omap_control_phy_power(phy->control_dev, 0);
145 static int ti_pipe3_power_on(struct phy *x)
147 struct ti_pipe3 *phy = phy_get_drvdata(x);
149 omap_control_phy_power(phy->control_dev, 1);
154 static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
162 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
168 dev_err(phy->dev, "DPLL failed to lock\n");
175 static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
180 dpll_params = ti_pipe3_get_dpll_params(phy);
184 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
187 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
189 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
192 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
194 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
197 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
199 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
202 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
204 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
207 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
209 ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
211 return ti_pipe3_dpll_wait_lock(phy);
214 static int ti_pipe3_init(struct phy *x)
216 struct ti_pipe3 *phy = phy_get_drvdata(x);
220 if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
221 omap_control_pcie_pcs(phy->control_dev, phy->id, 0xF1);
226 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
229 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
230 ret = ti_pipe3_dpll_wait_lock(phy);
234 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
236 if (ti_pipe3_dpll_program(phy))
242 static int ti_pipe3_exit(struct phy *x)
244 struct ti_pipe3 *phy = phy_get_drvdata(x);
251 if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") ||
252 of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
256 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
258 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
264 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
270 dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
291 struct ti_pipe3 *phy;
292 struct phy *generic_phy;
301 phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
302 if (!phy)
305 phy->dev = &pdev->dev;
307 if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
313 phy->dpll_map = (struct pipe3_dpll_map *)match->data;
314 if (!phy->dpll_map) {
321 phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
322 if (IS_ERR(phy->pll_ctrl_base))
323 return PTR_ERR(phy->pll_ctrl_base);
325 phy->sys_clk = devm_clk_get(phy->dev, "sysclk");
326 if (IS_ERR(phy->sys_clk)) {
332 if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
333 phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
334 if (IS_ERR(phy->wkupclk)) {
336 return PTR_ERR(phy->wkupclk);
339 phy->refclk = devm_clk_get(phy->dev, "refclk");
340 if (IS_ERR(phy->refclk)) {
342 return PTR_ERR(phy->refclk);
345 phy->wkupclk = ERR_PTR(-ENODEV);
346 phy->refclk = ERR_PTR(-ENODEV);
349 if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
350 if (of_property_read_u8(node, "id", &phy->id) < 0)
351 phy->id = 1;
353 clk = devm_clk_get(phy->dev, "dpll_ref");
360 clk = devm_clk_get(phy->dev, "dpll_ref_m2");
367 clk = devm_clk_get(phy->dev, "phy-div");
369 dev_err(&pdev->dev, "unable to get phy-div clk\n");
374 phy->div_clk = devm_clk_get(phy->dev, "div-clk");
375 if (IS_ERR(phy->div_clk)) {
377 return PTR_ERR(phy->div_clk);
380 phy->div_clk = ERR_PTR(-ENODEV);
395 phy->control_dev = &control_pdev->dev;
397 omap_control_phy_power(phy->control_dev, 0);
399 platform_set_drvdata(pdev, phy);
400 pm_runtime_enable(phy->dev);
402 generic_phy = devm_phy_create(phy->dev, NULL, &ops, NULL);
406 phy_set_drvdata(generic_phy, phy);
407 phy_provider = devm_of_phy_provider_register(phy->dev,
430 struct ti_pipe3 *phy = dev_get_drvdata(dev);
432 if (!IS_ERR(phy->wkupclk))
433 clk_disable_unprepare(phy->wkupclk);
434 if (!IS_ERR(phy->refclk))
435 clk_disable_unprepare(phy->refclk);
436 if (!IS_ERR(phy->div_clk))
437 clk_disable_unprepare(phy->div_clk);
445 struct ti_pipe3 *phy = dev_get_drvdata(dev);
447 if (!IS_ERR(phy->refclk)) {
448 ret = clk_prepare_enable(phy->refclk);
450 dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
455 if (!IS_ERR(phy->wkupclk)) {
456 ret = clk_prepare_enable(phy->wkupclk);
458 dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
463 if (!IS_ERR(phy->div_clk)) {
464 ret = clk_prepare_enable(phy->div_clk);
466 dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
473 if (!IS_ERR(phy->wkupclk))
474 clk_disable_unprepare(phy->wkupclk);
477 if (!IS_ERR(phy->refclk))
478 clk_disable_unprepare(phy->refclk);
497 .compatible = "ti,phy-usb3",
505 .compatible = "ti,phy-pipe3-sata",
509 .compatible = "ti,phy-pipe3-pcie",
530 MODULE_DESCRIPTION("TI PIPE3 phy driver");