Cross Reference: /drivers/pinctrl/sirf/pinctrl-sirf.c

Lines Matching refs:bank
444 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
449 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
461 				    struct sirfsoc_gpio_bank *bank,
467 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
483 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
485 	__sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
492 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
497 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
513 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
518 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
574 	struct sirfsoc_gpio_bank *bank;
581 		bank = &sgpio->sgpio_bank[i];
582 		if (bank->parent_irq == irq)
589 	status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
593 			__func__, bank->id, status);
599 		ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
607 				__func__, bank->id, idx);
609 					bank->id * SIRFSOC_GPIO_BANK_SIZE));
632 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
638 	spin_lock_irqsave(&bank->lock, flags);
644 	sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
645 	__sirfsoc_gpio_irq_mask(sgpio, bank, offset);
647 	spin_unlock_irqrestore(&bank->lock, flags);
655 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
658 	spin_lock_irqsave(&bank->lock, flags);
660 	__sirfsoc_gpio_irq_mask(sgpio, bank, offset);
661 	sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
663 	spin_unlock_irqrestore(&bank->lock, flags);
671 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
676 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
678 	spin_lock_irqsave(&bank->lock, flags);
682 	spin_unlock_irqrestore(&bank->lock, flags);
688 					   struct sirfsoc_gpio_bank *bank,
695 	spin_lock_irqsave(&bank->lock, flags);
707 	spin_unlock_irqrestore(&bank->lock, flags);
714 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
719 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
723 	sirfsoc_gpio_set_output(sgpio, bank, offset, value);
733 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
737 	spin_lock_irqsave(&bank->lock, flags);
739 	val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
741 	spin_unlock_irqrestore(&bank->lock, flags);
750 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
754 	spin_lock_irqsave(&bank->lock, flags);
756 	ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
761 	writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
763 	spin_unlock_irqrestore(&bank->lock, flags);
804 	struct sirfsoc_gpio_bank *bank;
860 		bank = &sgpio->sgpio_bank[i];
861 		spin_lock_init(&bank->lock);
862 		bank->parent_irq = platform_get_irq(pdev, i);
863 		if (bank->parent_irq < 0) {
864 			err = bank->parent_irq;
870 			bank->parent_irq,