Lines Matching refs:ret
182 int ret;
189 ret = intel_msic_reg_write(INTEL_MSIC_ADC1CNTL3, MSIC_ADCRRDATA_ENBL);
190 if (ret)
191 return ret;
194 ret = intel_msic_reg_write(INTEL_MSIC_ADC1CNTL3, MSIC_ADCTHERM_ENBL);
195 if (ret)
196 return ret;
199 ret = intel_msic_reg_read(addr, &data);
200 if (ret)
201 return ret;
207 ret = intel_msic_reg_read(addr, &data);/* Read lower bits */
208 if (ret)
209 return ret;
216 ret = adc_to_temp(td_info->direct, adc_val, &curr_temp);
217 if (ret == 0)
219 return ret;
232 int ret;
235 ret = intel_msic_reg_read(INTEL_MSIC_ADC1CNTL1, &data);
236 if (ret)
237 return ret;
259 int ret;
262 ret = intel_msic_reg_write(base_addr, SKIN_SENSOR0_CODE);
263 if (ret)
264 return ret;
266 ret = intel_msic_reg_write(base_addr + 1, SKIN_SENSOR1_CODE);
267 if (ret)
268 return ret;
270 ret = intel_msic_reg_write(base_addr + 2, SYS_SENSOR_CODE);
271 if (ret)
272 return ret;
276 ret = intel_msic_reg_write(base_addr + 3,
278 if (ret)
279 return ret;
293 int ret;
295 ret = intel_msic_reg_read(addr, &data);
296 if (ret)
297 return ret;
317 int ret;
322 ret = intel_msic_reg_read(INTEL_MSIC_ADC1CNTL1, &data);
323 if (ret)
324 return ret;
331 ret = intel_msic_reg_read(ADC_CHNL_START_ADDR + i, &data);
332 if (ret)
333 return ret;
336 ret = i;
340 return (ret > ADC_LOOP_MAX) ? (-EINVAL) : ret;
353 int ret;
359 ret = intel_msic_reg_read(INTEL_MSIC_ADC1CNTL3, &data);
360 if (ret)
361 return ret;
364 ret = intel_msic_reg_write(INTEL_MSIC_ADC1CNTL3, data);
365 if (ret)
366 return ret;
379 ret = reset_stopbit(base_addr);
380 if (ret)
381 return ret;
388 ret = set_up_therm_channel(base_addr);
389 if (ret) {
391 return ret;
394 return ret;
480 int ret;
490 ret = mid_initialize_adc(&pdev->dev);
491 if (ret) {
493 return ret;
501 ret = -ENOMEM;
508 ret = PTR_ERR(pinfo->tzd[i]);
523 return ret;