Cross Reference: /drivers/spi/spi-fsl-spi.c

Lines Matching refs:reg_base
90 	struct fsl_spi_reg *reg_base = mspi->reg_base;
91 	__be32 __iomem *mode = &reg_base->mode;
292 	struct fsl_spi_reg *reg_base = mspi->reg_base;
297 	mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
301 	mpc8xxx_spi_write_reg(&reg_base->transmit, word);
310 	struct fsl_spi_reg *reg_base;
315 	reg_base = mpc8xxx_spi->reg_base;
348 	mpc8xxx_spi_write_reg(&reg_base->mask, 0);
425 	struct fsl_spi_reg *reg_base;
441 	reg_base = mpc8xxx_spi->reg_base;
444 	cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
510 	struct fsl_spi_reg *reg_base = mspi->reg_base;
514 		u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
523 			mpc8xxx_spi_read_reg(&reg_base->event)) &
528 	mpc8xxx_spi_write_reg(&reg_base->event, events);
534 		mpc8xxx_spi_write_reg(&reg_base->transmit, word);
545 	struct fsl_spi_reg *reg_base = mspi->reg_base;
548 	events = mpc8xxx_spi_read_reg(&reg_base->event);
564 	iounmap(mspi->reg_base);
571 	struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
578 		slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
580 		mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
589 	struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
593 	capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
603 		mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
615 	struct fsl_spi_reg *reg_base;
644 	mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
645 	if (mpc8xxx_spi->reg_base == NULL) {
672 	reg_base = mpc8xxx_spi->reg_base;
675 	mpc8xxx_spi_write_reg(&reg_base->mode, 0);
676 	mpc8xxx_spi_write_reg(&reg_base->mask, 0);
677 	mpc8xxx_spi_write_reg(&reg_base->command, 0);
678 	mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
689 	mpc8xxx_spi_write_reg(&reg_base->mode, regval);
695 	dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
703 	iounmap(mpc8xxx_spi->reg_base);