Cross Reference: /drivers/tty/serial/amba-pl010.c

Lines Matching refs:membase
81 	cr = readb(uap->port.membase + UART010_CR);
83 	writel(cr, uap->port.membase + UART010_CR);
91 	cr = readb(uap->port.membase + UART010_CR);
93 	writel(cr, uap->port.membase + UART010_CR);
101 	cr = readb(uap->port.membase + UART010_CR);
103 	writel(cr, uap->port.membase + UART010_CR);
111 	cr = readb(uap->port.membase + UART010_CR);
113 	writel(cr, uap->port.membase + UART010_CR);
120 	status = readb(uap->port.membase + UART01x_FR);
122 		ch = readb(uap->port.membase + UART01x_DR);
131 		rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
133 			writel(0, uap->port.membase + UART01x_ECR);
163 		status = readb(uap->port.membase + UART01x_FR);
176 		writel(uap->port.x_char, uap->port.membase + UART01x_DR);
188 		writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
206 	writel(0, uap->port.membase + UART010_ICR);
208 	status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
236 	status = readb(uap->port.membase + UART010_IIR);
249 			status = readb(uap->port.membase + UART010_IIR);
263 	unsigned int status = readb(uap->port.membase + UART01x_FR);
273 	status = readb(uap->port.membase + UART01x_FR);
289 		uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl);
299 	lcr_h = readb(uap->port.membase + UART010_LCRH);
304 	writel(lcr_h, uap->port.membase + UART010_LCRH);
332 	uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
338 	       uap->port.membase + UART010_CR);
360 	writel(0, uap->port.membase + UART010_CR);
363 	writel(readb(uap->port.membase + UART010_LCRH) &
365 	       uap->port.membase + UART010_LCRH);
448 	old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
453 	writel(0, uap->port.membase + UART010_CR);
457 	writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
458 	writel(quot & 0xff, uap->port.membase + UART010_LCRL);
465 	writel(lcr_h, uap->port.membase + UART010_LCRH);
466 	writel(old_cr, uap->port.membase + UART010_CR);
558 		status = readb(uap->port.membase + UART01x_FR);
561 	writel(ch, uap->port.membase + UART01x_DR);
575 	old_cr = readb(uap->port.membase + UART010_CR);
576 	writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
585 		status = readb(uap->port.membase + UART01x_FR);
588 	writel(old_cr, uap->port.membase + UART010_CR);
597 	if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
599 		lcr_h = readb(uap->port.membase + UART010_LCRH);
614 		quot = readb(uap->port.membase + UART010_LCRL) |
615 		       readb(uap->port.membase + UART010_LCRM) << 8;
709 	uap->port.membase = base;